forked from M-Labs/artiq
serwb: add generic low-speed phy (125Mhz linerate, same phy for ultrascale/7-series)
This commit is contained in:
Florent Kermarrec
parent
520aade8fe
commit
913d1e8e12
@ -1 +1 @@
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from artiq.gateware.serwb import s7phy, kusphy, phy, core, packet, etherbone
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from artiq.gateware.serwb import s7phy, kusphy, genphy, phy, core, packet, etherbone
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418
artiq/gateware/serwb/genphy.py
Normal file
418
artiq/gateware/serwb/genphy.py
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from migen import *
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from migen.genlib.io import *
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from migen.genlib.misc import BitSlip, WaitTimer
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from misoc.interconnect import stream
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from misoc.interconnect.csr import *
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from misoc.cores.code_8b10b import Encoder, Decoder
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from artiq.gateware.serwb.scrambler import Scrambler, Descrambler
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def K(x, y):
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return (y << 5) | x
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class _SerdesClocking(Module):
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def __init__(self, pads, mode="master"):
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self.refclk = Signal()
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# # #
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# In Master mode, generate the clock with 180° phase shift so that Slave
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# can use this clock to sample data
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if mode == "master":
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self.specials += DDROutput(0, 1, self.refclk)
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self.specials += DifferentialOutput(self.refclk, pads.clk_p, pads.clk_n)
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# In Slave mode, use the clock provided by Master
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elif mode == "slave":
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self.specials += DifferentialInput(pads.clk_p, pads.clk_n, self.refclk)
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class _SerdesTX(Module):
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def __init__(self, pads, mode="master"):
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# Control
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self.idle = idle = Signal()
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self.comma = comma = Signal()
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# Datapath
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self.ce = ce = Signal()
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self.k = k = Signal(4)
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self.d = d = Signal(32)
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# # #
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# 8b10b encoder
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self.submodules.encoder = encoder = CEInserter()(Encoder(4, True))
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self.comb += encoder.ce.eq(ce)
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# 40 --> 1 converter
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converter = stream.Converter(40, 1)
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self.submodules += converter
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self.comb += [
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converter.sink.stb.eq(1),
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converter.source.ack.eq(1),
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# Enable pipeline when converter accepts the 40 bits
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ce.eq(converter.sink.ack),
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# If not idle, connect encoder to converter
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If(~idle,
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converter.sink.data.eq(Cat(*[encoder.output[i] for i in range(4)]))
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),
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# If comma, send K28.5
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If(comma,
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encoder.k[0].eq(1),
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encoder.d[0].eq(K(28,5)),
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# Else connect TX to encoder
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).Else(
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encoder.k[0].eq(k[0]),
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encoder.k[1].eq(k[1]),
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encoder.k[2].eq(k[2]),
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encoder.k[3].eq(k[3]),
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encoder.d[0].eq(d[0:8]),
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encoder.d[1].eq(d[8:16]),
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encoder.d[2].eq(d[16:24]),
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encoder.d[3].eq(d[24:32])
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)
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]
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# Data output (on rising edge of sys_clk)
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data = Signal()
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self.sync += data.eq(converter.source.data)
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self.specials += DifferentialOutput(data, pads.tx_p, pads.tx_n)
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class _SerdesRX(Module):
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def __init__(self, pads, mode="master"):
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# Control
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self.bitslip_value = bitslip_value = Signal(6)
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# Status
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self.idle = idle = Signal()
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self.comma = comma = Signal()
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# Datapath
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self.ce = ce = Signal()
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self.k = k = Signal(4)
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self.d = d = Signal(32)
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# # #
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# Input data (on rising edge of sys_clk)
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data = Signal()
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data_d = Signal()
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self.specials += DifferentialInput(pads.rx_p, pads.rx_n, data)
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self.sync += data_d.eq(data)
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# 1 --> 40 converter and bitslip
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converter = stream.Converter(1, 40)
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self.submodules += converter
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bitslip = CEInserter()(BitSlip(40))
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self.submodules += bitslip
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self.comb += [
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converter.sink.stb.eq(1),
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converter.source.ack.eq(1),
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# Enable pipeline when converter outputs the 40 bits
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ce.eq(converter.source.stb),
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# Connect input data to converter
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converter.sink.data.eq(data),
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# Connect converter to bitslip
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bitslip.ce.eq(ce),
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bitslip.value.eq(bitslip_value),
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bitslip.i.eq(converter.source.data)
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]
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# 8b10b decoder
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self.submodules.decoders = decoders = [CEInserter()(Decoder(True)) for _ in range(4)]
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self.comb += [decoders[i].ce.eq(ce) for i in range(4)]
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self.comb += [
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# Connect bitslip to decoder
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decoders[0].input.eq(bitslip.o[0:10]),
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decoders[1].input.eq(bitslip.o[10:20]),
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decoders[2].input.eq(bitslip.o[20:30]),
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decoders[3].input.eq(bitslip.o[30:40]),
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# Connect decoder to output
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self.k.eq(Cat(*[decoders[i].k for i in range(4)])),
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self.d.eq(Cat(*[decoders[i].d for i in range(4)])),
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]
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# Status
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idle_timer = WaitTimer(256)
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self.submodules += idle_timer
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self.comb += [
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idle_timer.wait.eq(1),
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self.idle.eq(idle_timer.done &
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((bitslip.o == 0) | (bitslip.o == (2**40-1)))),
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self.comma.eq(
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(decoders[0].k == 1) & (decoders[0].d == K(28,5)) &
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(decoders[1].k == 0) & (decoders[1].d == 0) &
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(decoders[2].k == 0) & (decoders[2].d == 0) &
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(decoders[3].k == 0) & (decoders[3].d == 0))
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]
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@ResetInserter()
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class _Serdes(Module):
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def __init__(self, pads, mode="master"):
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self.submodules.clocking = _SerdesClocking(pads, mode)
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self.submodules.tx = _SerdesTX(pads, mode)
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self.submodules.rx = _SerdesRX(pads, mode)
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# SERWB Master <--> Slave physical synchronization process:
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# 1) Master sends idle patterns (zeroes) to Slave to reset it.
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# 2) Master sends K28.5 commas to allow Slave to calibrate, Slave sends idle patterns.
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# 3) Slave sends K28.5 commas to allow Master to calibrate, Master sends K28.5 commas.
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# 4) Master stops sending K28.5 commas.
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# 5) Slave stops sending K28.5 commas.
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# 6) Physical link is ready.
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@ResetInserter()
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class _SerdesMasterInit(Module):
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def __init__(self, serdes, timeout):
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self.ready = Signal()
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self.error = Signal()
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# # #
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self.bitslip = bitslip = Signal(max=40)
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self.submodules.timer = timer = WaitTimer(timeout)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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NextValue(bitslip, 0),
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NextState("RESET_SLAVE"),
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serdes.tx.idle.eq(1)
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)
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fsm.act("RESET_SLAVE",
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timer.wait.eq(1),
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If(timer.done,
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timer.wait.eq(0),
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NextState("SEND_PATTERN")
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),
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serdes.tx.idle.eq(1)
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)
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fsm.act("SEND_PATTERN",
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If(~serdes.rx.idle,
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timer.wait.eq(1),
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If(timer.done,
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NextState("CHECK_PATTERN")
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)
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),
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serdes.tx.comma.eq(1)
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)
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fsm.act("WAIT_STABLE",
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timer.wait.eq(1),
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If(timer.done,
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timer.wait.eq(0),
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NextState("CHECK_PATTERN")
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),
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serdes.tx.comma.eq(1)
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)
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fsm.act("CHECK_PATTERN",
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If(serdes.rx.comma,
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timer.wait.eq(1),
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If(timer.done,
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NextState("READY")
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)
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).Else(
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NextState("INC_BITSLIP")
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),
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serdes.tx.comma.eq(1)
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)
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self.comb += serdes.rx.bitslip_value.eq(bitslip)
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fsm.act("INC_BITSLIP",
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NextState("WAIT_STABLE"),
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If(bitslip == (40 - 1),
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NextState("ERROR")
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).Else(
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NextValue(bitslip, bitslip + 1)
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),
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serdes.tx.comma.eq(1)
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)
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fsm.act("READY",
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self.ready.eq(1)
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)
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fsm.act("ERROR",
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self.error.eq(1)
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)
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@ResetInserter()
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class _SerdesSlaveInit(Module, AutoCSR):
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def __init__(self, serdes, timeout):
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self.ready = Signal()
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self.error = Signal()
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# # #
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self.bitslip = bitslip = Signal(max=40)
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self.submodules.timer = timer = WaitTimer(timeout)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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# reset
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fsm.act("IDLE",
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NextValue(bitslip, 0),
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timer.wait.eq(1),
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If(timer.done,
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timer.wait.eq(0),
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NextState("WAIT_STABLE"),
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),
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serdes.tx.idle.eq(1)
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)
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fsm.act("WAIT_STABLE",
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timer.wait.eq(1),
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If(timer.done,
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timer.wait.eq(0),
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NextState("CHECK_PATTERN")
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),
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serdes.tx.idle.eq(1)
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)
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fsm.act("CHECK_PATTERN",
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If(serdes.rx.comma,
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timer.wait.eq(1),
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If(timer.done,
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NextState("SEND_PATTERN")
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)
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).Else(
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NextState("INC_BITSLIP")
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),
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serdes.tx.idle.eq(1)
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)
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self.comb += serdes.rx.bitslip_value.eq(bitslip)
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fsm.act("INC_BITSLIP",
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NextState("WAIT_STABLE"),
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If(bitslip == (40 - 1),
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NextState("ERROR")
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).Else(
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NextValue(bitslip, bitslip + 1)
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),
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serdes.tx.idle.eq(1)
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)
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fsm.act("SEND_PATTERN",
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timer.wait.eq(1),
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If(timer.done,
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If(~serdes.rx.comma,
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NextState("READY")
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)
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),
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serdes.tx.comma.eq(1)
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)
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fsm.act("READY",
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self.ready.eq(1)
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)
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fsm.act("ERROR",
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self.error.eq(1)
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)
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class _SerdesControl(Module, AutoCSR):
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def __init__(self, serdes, init, mode="master"):
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if mode == "master":
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self.reset = CSR()
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self.ready = CSRStatus()
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self.error = CSRStatus()
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self.bitslip = CSRStatus(6)
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self.scrambling_enable = CSRStorage()
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self.prbs_error = Signal()
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self.prbs_start = CSR()
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self.prbs_cycles = CSRStorage(32)
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self.prbs_errors = CSRStatus(32)
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# # #
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if mode == "master":
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# In Master mode, reset is coming from CSR,
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# it resets the Master that will also reset
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# the Slave by putting the link in idle.
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self.sync += init.reset.eq(self.reset.re)
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else:
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# In Slave mode, reset is coming from link,
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# Master reset the Slave by putting the link
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# in idle.
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self.sync += [
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init.reset.eq(serdes.rx.idle),
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serdes.reset.eq(serdes.rx.idle)
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]
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self.comb += [
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self.ready.status.eq(init.ready),
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self.error.status.eq(init.error),
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self.bitslip.status.eq(init.bitslip)
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]
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# prbs
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prbs_cycles = Signal(32)
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prbs_errors = self.prbs_errors.status
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prbs_fsm = FSM(reset_state="IDLE")
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self.submodules += prbs_fsm
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prbs_fsm.act("IDLE",
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NextValue(prbs_cycles, 0),
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If(self.prbs_start.re,
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NextValue(prbs_errors, 0),
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NextState("CHECK")
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)
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)
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prbs_fsm.act("CHECK",
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NextValue(prbs_cycles, prbs_cycles + 1),
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If(self.prbs_error,
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NextValue(prbs_errors, prbs_errors + 1),
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),
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If(prbs_cycles == self.prbs_cycles.storage,
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NextState("IDLE")
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)
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)
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class SERWBPHY(Module, AutoCSR):
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def __init__(self, pads, mode="master", init_timeout=2**16):
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self.sink = sink = stream.Endpoint([("data", 32)])
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self.source = source = stream.Endpoint([("data", 32)])
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assert mode in ["master", "slave"]
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self.submodules.serdes = _Serdes(pads, mode)
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if mode == "master":
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self.submodules.init = _SerdesMasterInit(self.serdes, init_timeout)
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else:
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self.submodules.init = _SerdesSlaveInit(self.serdes, init_timeout)
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self.submodules.control = _SerdesControl(self.serdes, self.init, mode)
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# scrambling
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scrambler = Scrambler()
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descrambler = Descrambler()
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self.submodules += scrambler, descrambler
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self.comb += [
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scrambler.enable.eq(self.control.scrambling_enable.storage),
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descrambler.enable.eq(self.control.scrambling_enable.storage)
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]
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# tx dataflow
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self.comb += \
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If(self.init.ready,
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sink.connect(scrambler.sink),
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scrambler.source.ack.eq(self.serdes.tx.ce),
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If(scrambler.source.stb,
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self.serdes.tx.d.eq(scrambler.source.d),
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self.serdes.tx.k.eq(scrambler.source.k)
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)
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)
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# rx dataflow
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self.comb += [
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If(self.init.ready,
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descrambler.sink.stb.eq(self.serdes.rx.ce),
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descrambler.sink.d.eq(self.serdes.rx.d),
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descrambler.sink.k.eq(self.serdes.rx.k),
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descrambler.source.connect(source)
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),
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# For PRBS test we are using the scrambler/descrambler as PRBS,
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# sending 0 to the scrambler and checking that descrambler
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# output is always 0.
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self.control.prbs_error.eq(
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descrambler.source.stb &
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descrambler.source.ack &
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(descrambler.source.data != 0))
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]
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