diff --git a/artiq/gateware/rtio/phy/dds.py b/artiq/gateware/rtio/phy/dds.py
index 8568c57e1..37dab89f4 100644
--- a/artiq/gateware/rtio/phy/dds.py
+++ b/artiq/gateware/rtio/phy/dds.py
@@ -5,7 +5,7 @@ from artiq.gateware.rtio.phy.wishbone import RT2WB
 
 
 class _AD9xxx(Module):
-    def __init__(self, ftw_base, pads, nchannels, **kwargs):
+    def __init__(self, ftw_base, pads, nchannels, onehot=False, **kwargs):
         self.submodules._ll = RenameClockDomains(
             ad9xxx.AD9xxx(pads, **kwargs), "rio")
         self.submodules._rt2wb = RT2WB(flen(pads.a)+1, self._ll.bus)
@@ -21,23 +21,29 @@ class _AD9xxx(Module):
                             current_address.eq(self.rtlink.o.address),
                             current_data.eq(self.rtlink.o.data))
 
-        # keep track of the currently selected channel
-        current_channel = Signal(max=nchannels)
+        # keep track of the currently selected channel(s)
+        current_sel = Signal(flen(current_data)-1)
         self.sync.rio += If(current_address == 2**flen(pads.a) + 1,
-                            current_channel.eq(current_data))
+                            current_sel.eq(current_data[1:]))  # strip reset
+
+        def selected(c):
+            if onehot:
+                return current_sel[c]
+            else:
+                return current_sel == c
 
         # keep track of frequency tuning words, before they are FUDed
         ftws = [Signal(32) for i in range(nchannels)]
         for c, ftw in enumerate(ftws):
             if flen(pads.d) == 8:
                 self.sync.rio += \
-                    If(current_channel == c, [
+                    If(selected(c), [
                         If(current_address == ftw_base+i,
                            ftw[i*8:(i+1)*8].eq(current_data))
                         for i in range(4)])
             elif flen(pads.d) == 16:
                 self.sync.rio += \
-                    If(current_channel == c, [
+                    If(selected(c), [
                         If(current_address == ftw_base+2*i,
                            ftw[i*16:(i+1)*16].eq(current_data))
                         for i in range(2)])
@@ -46,15 +52,15 @@ class _AD9xxx(Module):
 
         # FTW to probe on FUD
         self.sync.rio += If(current_address == 2**flen(pads.a), [
-            If(current_channel == c, probe.eq(ftw))
+            If(selected(c), probe.eq(ftw))
             for c, (probe, ftw) in enumerate(zip(self.probes, ftws))])
 
 
 class AD9858(_AD9xxx):
-    def __init__(self, pads, nchannels, **kwargs):
-        _AD9xxx.__init__(self, 0x0a, pads, nchannels, **kwargs)
+    def __init__(self, *args, **kwargs):
+        _AD9xxx.__init__(self, 0x0a, *args, **kwargs)
 
 
 class AD9914(_AD9xxx):
-    def __init__(self, pads, nchannels, **kwargs):
-        _AD9xxx.__init__(self, 0x2d, pads, nchannels, **kwargs)
+    def __init__(self, *args, **kwargs):
+        _AD9xxx.__init__(self, 0x2d, *args, **kwargs)
diff --git a/soc/targets/artiq_kc705.py b/soc/targets/artiq_kc705.py
index 1ffc83aea..a548d98dc 100644
--- a/soc/targets/artiq_kc705.py
+++ b/soc/targets/artiq_kc705.py
@@ -206,7 +206,7 @@ class NIST_QC2(_NIST_QCx):
         self.add_constant("DDS_CHANNEL_COUNT", 11)
         self.add_constant("DDS_AD9914")
         self.add_constant("DDS_ONEHOT_SEL")
-        phy = dds.AD9914(platform.request("dds"), 11)
+        phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy,
                                                    ofifo_depth=512,