forked from M-Labs/artiq
satellite: add dma to gateware
This commit is contained in:
parent
d0437f5672
commit
90a6fe1c35
|
@ -567,8 +567,10 @@ class SatelliteBase(BaseSoC):
|
|||
|
||||
self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels, lane_count=sed_lanes)
|
||||
self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
|
||||
self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if(), self.cpu_dw)
|
||||
self.csr_devices.append("rtio_dma")
|
||||
self.submodules.cri_con = rtio.CRIInterconnectShared(
|
||||
[self.drtiosat.cri],
|
||||
[self.drtiosat.cri, self.rtio_dma.cri],
|
||||
[self.local_io.cri] + self.drtio_cri,
|
||||
enable_routing=True)
|
||||
self.csr_devices.append("cri_con")
|
||||
|
|
|
@ -451,8 +451,10 @@ class _SatelliteBase(BaseSoC):
|
|||
|
||||
self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
|
||||
self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
|
||||
self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if(), self.cpu_dw)
|
||||
self.csr_devices.append("rtio_dma")
|
||||
self.submodules.cri_con = rtio.CRIInterconnectShared(
|
||||
[self.drtiosat.cri],
|
||||
[self.drtiosat.cri, self.rtio_dma.cri],
|
||||
[self.local_io.cri] + self.drtio_cri,
|
||||
enable_routing=True)
|
||||
self.csr_devices.append("cri_con")
|
||||
|
|
Loading…
Reference in New Issue