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aqctl_corelog: fix endianness issue (closes #1682) (#1689) 

Fixed according to
https://forum.m-labs.hk/d/190-fetchingreading-the-core-log-in-a-central-location/10

Tested with both KC705 and ZC706.
This commit is contained in:
pca006132 2021-06-03 14:06:17 +08:00 committed by Sebastien Bourdeauducq
parent a80c35a606
commit 9033c59b75
1 changed files with 8 additions and 1 deletions
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9
artiq/frontend/aqctl_corelog.py
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@ -39,11 +39,18 @@ async def get_logs_sim(host):
async def get_logs(host): async def get_logs(host):
reader, writer = await asyncio.open_connection(host, 1380) reader, writer = await asyncio.open_connection(host, 1380)
writer.write(b"ARTIQ management\n") writer.write(b"ARTIQ management\n")
endian = await reader.readexactly(1)
if endian == b"e":
endian = "<"
elif endian == b"E":
endian = ">"
else:
raise IOError("Incorrect reply from device: expected e/E.")
writer.write(struct.pack("B", Request.PullLog.value)) writer.write(struct.pack("B", Request.PullLog.value))
await writer.drain() await writer.drain()
while True: while True:
length, = struct.unpack(">l", await reader.readexactly(4)) length, = struct.unpack(endian + "l", await reader.readexactly(4))
log = await reader.readexactly(length) log = await reader.readexactly(length)
for line in log.decode("utf-8").splitlines(): for line in log.decode("utf-8").splitlines():