From 900b0cc6296795a57dd6e7d19005c245c2efe1f5 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 19 Mar 2016 19:40:23 +0800 Subject: [PATCH] analyzer: make byte_count 64-bit --- artiq/gateware/rtio/analyzer.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/rtio/analyzer.py b/artiq/gateware/rtio/analyzer.py index 37b15bdfd..cb927b740 100644 --- a/artiq/gateware/rtio/analyzer.py +++ b/artiq/gateware/rtio/analyzer.py @@ -165,7 +165,7 @@ class DMAWriter(Module, AutoCSR): alignment_bits=data_alignment) self.last_address = CSRStorage(aw + data_alignment, alignment_bits=data_alignment) - self.byte_count = CSRStatus(32) # only read when shut down + self.byte_count = CSRStatus(64) # only read when shut down self.sink = stream.Endpoint( [("data", dw), @@ -199,7 +199,7 @@ class DMAWriter(Module, AutoCSR): ) ] - message_count = Signal(32 - log2_int(message_len//8)) + message_count = Signal(64 - log2_int(message_len//8)) self.comb += self.byte_count.status.eq( message_count << log2_int(message_len//8)) self.sync += [