From 8fe463d4a0b73f3badfcc2b7264788fd7088336b Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 20 Jan 2018 06:02:05 +0100
Subject: [PATCH] sayma_rtm: add UART loopback to easily know if rtm fpga is
 alive

---
 artiq/gateware/targets/sayma_rtm.py | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py
index 5861be3e8..338019044 100755
--- a/artiq/gateware/targets/sayma_rtm.py
+++ b/artiq/gateware/targets/sayma_rtm.py
@@ -93,6 +93,10 @@ class SaymaRTM(Module):
             platform.request("dac_clk_src_sel")))
         csr_devices.append("clock_mux")
 
+        # UART loopback
+        serial = platform.request(serial)
+        self.comb += serial.tx.eq(serial.rx)
+
         # Allaki: enable RF output, GPIO access to attenuator
         self.comb += [
             platform.request("allaki0_rfsw0").eq(1),