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pipistrello: sys_clk 83 -> 75 MHz 

This should close #341 once migen generates stable output.
This commit is contained in:
Robert Jördens 2016-03-21 13:47:32 +01:00
parent 22cd12f721
commit 8f54a1e619
1 changed files with 1 additions and 0 deletions
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artiq/gateware/targets/pipistrello.py
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@ -147,6 +147,7 @@ class NIST_QC1(BaseSoC, AMPSoC):
l2_size=64*1024, l2_size=64*1024,
with_timer=False, with_timer=False,
ident=artiq_version, ident=artiq_version,
clk_freq=75*1000*1000,
**kwargs) **kwargs)
AMPSoC.__init__(self) AMPSoC.__init__(self)