forked from M-Labs/artiq
rtio/sed: add FIFO wrapper
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490c9815a2
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8e5ab90129
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@ -0,0 +1,37 @@
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from migen import *
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from migen.genlib.fifo import *
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from artiq.gateware.rtio.sed import layouts
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__all__ = ["FIFO"]
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class FIFO(Module):
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def __init__(self, lane_count, mode, fifo_depth, layout_payload):
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seqn_width = layouts.seqn_width(lane_count, fifo_width)
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self.input = [layouts.fifo_ingress(seqn_width, layout_payload)
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for _ in range(lane_count)]
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self.output = [layouts.fifo_egress(seqn_width, layout_payload)
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for _ in range(lane_count)]
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if mode == "sync":
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fifo_cls = fifo.SyncFIFOBuffered
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elif mode == "async":
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fifo_cls = fifo.AsyncFIFO
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else:
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raise ValueError
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for input, output in zip(self.input, self.output):
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fifo = fifo_cls(layout_len(layout_payload), fifo_depth)
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self.submodules += fifo
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self.comb += [
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fifo.din.eq(input.payload.raw_bits()),
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fifo.we.eq(input.we),
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input.writable.eq(fifo.writable),
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output.payload.raw_bits().eq(fifo.dout),
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output.readable.eq(fifo.readable),
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fifo.re.eq(output.re)
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]
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@ -14,14 +14,10 @@ __all__ = ["LaneDistributor"]
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# 3. check status
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class LaneDistributor(Module):
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def __init__(self, lane_count, fifo_size, layout_payload, fine_ts_width, enable_spread=True):
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def __init__(self, lane_count, seqn_width, layout_payload, fine_ts_width, enable_spread=True):
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if lane_count & (lane_count - 1):
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raise NotImplementedError("lane count must be a power of 2")
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# There must be a unique sequence number for every possible event in every FIFO.
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# Plus 2 bits to detect and handle wraparounds.
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seqn_width = bits_for(lane_count*fifo_size-1) + 2
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self.cri = cri.Interface()
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self.minimum_coarse_timestamp = Signal(64-fine_ts_width)
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self.lane_io = [Record(layouts.fifo_ingress(seqn_width, layout_payload))
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@ -21,6 +21,12 @@ def fifo_payload(channels):
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return layout
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def seqn_width(lane_count, fifo_width):
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# There must be a unique sequence number for every possible event in every FIFO.
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# Plus 2 bits to detect and handle wraparounds.
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return bits_for(lane_count*fifo_size-1) + 2
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def fifo_ingress(seqn_width, layout_payload):
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return [
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("we", 1, DIR_M_TO_S),
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@ -10,7 +10,7 @@ LANE_COUNT = 8
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def simulate(input_events, wait=True):
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dut = lane_distributor.LaneDistributor(LANE_COUNT, 16, [("channel", 8), ("timestamp", 32)], 3)
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dut = lane_distributor.LaneDistributor(LANE_COUNT, 8, [("channel", 8), ("timestamp", 32)], 3)
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output = []
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access_results = []
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