forked from M-Labs/artiq
AD9912: Add PLL bypass option (pll_en) like AD9910
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@ -25,12 +25,14 @@ class AD9912:
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f_ref/clk_div*pll_n where f_ref is the reference frequency and clk_div
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is the reference clock divider (both set in the parent Urukul CPLD
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instance).
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:param pll_en: PLL enable bit, set to 0 to bypass PLL (default: 1).
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Note that when bypassing the PLL the red front panel LED may remain on.
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"""
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def __init__(self, dmgr, chip_select, cpld_device, sw_device=None,
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pll_n=10):
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pll_n=10, pll_en=1):
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self.kernel_invariants = {"cpld", "core", "bus", "chip_select",
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"pll_n", "ftw_per_hz"}
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"pll_n", "pll_en", "ftw_per_hz"}
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self.cpld = dmgr.get(cpld_device)
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self.core = self.cpld.core
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self.bus = self.cpld.bus
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@ -39,8 +41,12 @@ class AD9912:
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if sw_device:
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self.sw = dmgr.get(sw_device)
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self.kernel_invariants.add("sw")
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self.pll_en = pll_en
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self.pll_n = pll_n
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sysclk = self.cpld.refclk / [1, 1, 2, 4][self.cpld.clk_div] * pll_n
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if pll_en:
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sysclk = self.cpld.refclk / [1, 1, 2, 4][self.cpld.clk_div] * pll_n
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else:
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sysclk = self.cpld.refclk
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assert sysclk <= 1e9
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self.ftw_per_hz = 1 / sysclk * (int64(1) << 48)
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@ -102,13 +108,15 @@ class AD9912:
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raise ValueError("Urukul AD9912 product id mismatch")
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delay(50 * us)
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# HSTL power down, CMOS power down
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self.write(AD9912_PWRCNTRL1, 0x80, length=1)
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self.cpld.io_update.pulse(2 * us)
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self.write(AD9912_N_DIV, self.pll_n // 2 - 2, length=1)
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self.cpld.io_update.pulse(2 * us)
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# I_cp = 375 µA, VCO high range
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self.write(AD9912_PLLCFG, 0b00000101, length=1)
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pwrcntrl1 = 0x80 | ((~self.pll_en & 1) << 4)
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self.write(AD9912_PWRCNTRL1, pwrcntrl1, length=1)
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self.cpld.io_update.pulse(2 * us)
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if self.pll_en:
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self.write(AD9912_N_DIV, self.pll_n // 2 - 2, length=1)
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self.cpld.io_update.pulse(2 * us)
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# I_cp = 375 µA, VCO high range
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self.write(AD9912_PLLCFG, 0b00000101, length=1)
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self.cpld.io_update.pulse(2 * us)
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delay(1 * ms)
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@kernel
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