From 8d59f843fba2e53699bc70992bc0212c0405be52 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 21 Nov 2014 16:39:22 -0800 Subject: [PATCH] doc/manual: add FPGA board info and TTL line assignments --- doc/manual/fpga_board_ports.rst | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 doc/manual/fpga_board_ports.rst diff --git a/doc/manual/fpga_board_ports.rst b/doc/manual/fpga_board_ports.rst new file mode 100644 index 000000000..e74f5d312 --- /dev/null +++ b/doc/manual/fpga_board_ports.rst @@ -0,0 +1,26 @@ +FPGA board ports +================ + +KC705 +----- + +The main target board for the ARTIQ core device is the KC705 development board from Xilinx. + +Papilio Pro +----------- + +The low-cost Papilio Pro FPGA board can be used with some limitations. + +When plugged to a QC-DAQ LVDS adapter, the AD9858 DDS hardware can be used in addition to a limited number of TTL channels. The TTL lines are mapped to RTIO channels as follows: + ++--------------+----------+----------------+ +| RTIO channel | TTL line | Capability | ++==============+==========+================+ +| 0 | PMT0 | Output + input | ++--------------+----------+----------------+ +| 1 | TTL0 | Output only | ++--------------+----------+----------------+ +| 2 | TTL1 | Output only | ++--------------+----------+----------------+ +| 3 | TTL2 | Output only | ++--------------+----------+----------------+