forked from M-Labs/artiq
rtio/sed: fix sequence number width computation
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@ -25,7 +25,9 @@ class LaneDistributor(Module):
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if lane_count & (lane_count - 1):
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raise NotImplementedError("lane count must be a power of 2")
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seqn_width = 4*bits_for(lane_count*fifo_size-1)
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# There must be a unique sequence number for every possible event in every FIFO.
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# Plus 2 bits to detect and handle wraparounds.
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seqn_width = bits_for(lane_count*fifo_size-1) + 2
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self.cri = cri.Interface()
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self.minimum_coarse_timestamp = Signal(64-fine_ts_width)
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