From 8c1390e5570422ece2d37d41bc7c47671533d8c6 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 12 May 2018 22:57:34 +0800 Subject: [PATCH] kasli: use 62.5MHz clock for siphaser reference (#999) --- artiq/gateware/targets/kasli.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index a1cb3dda2..14c1b9448 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -934,7 +934,8 @@ class _SatelliteBase(BaseSoC): self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("si5324_clkin"), - si5324_clkout_fabric=platform.request("si5324_clkout_fabric")) + si5324_clkout_fabric=platform.request("si5324_clkout_fabric"), + ref_clk=self.crg.clk125_div2, ref_div2=True) platform.add_false_path_constraints( self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.csr_devices.append("siphaser")