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artiq
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just &1 to stay in field

This commit is contained in:
SingularitySurfer 2022-06-21 08:43:55 +00:00
parent 0388161754
commit 8bea821f93
1 changed files with 1 additions and 6 deletions
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7
artiq/coredevice/phaser.py
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@ -1071,12 +1071,7 @@ class PhaserChannel:
if (profile < 0) or (profile > 3): if (profile < 0) or (profile > 3):
raise ValueError("invalid profile index") raise ValueError("invalid profile index")
addr = PHASER_ADDR_SERVO_CFG0 + self.index addr = PHASER_ADDR_SERVO_CFG0 + self.index
data = 0 data = (profile << 2) | ((hold & 1) << 1) | (~bypass & 1)
if bypass == 0:
data = 1
if hold == 1:
data = data | (1 << 1)
data = data | (profile << 2)
self.phaser.write8(addr, data) self.phaser.write8(addr, data)
@kernel @kernel