forked from M-Labs/artiq
just &1 to stay in field
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@ -1071,12 +1071,7 @@ class PhaserChannel:
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if (profile < 0) or (profile > 3):
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raise ValueError("invalid profile index")
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addr = PHASER_ADDR_SERVO_CFG0 + self.index
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data = 0
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if bypass == 0:
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data = 1
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if hold == 1:
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data = data | (1 << 1)
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data = data | (profile << 2)
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data = (profile << 2) | ((hold & 1) << 1) | (~bypass & 1)
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self.phaser.write8(addr, data)
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@kernel
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