srenblad/artiq
1
0
Fork 0
forked from M-Labs/artiq
Code Pull Requests Activity

just &1 to stay in field

Browse Source
This commit is contained in:
SingularitySurfer 2022-06-21 08:43:55 +00:00
parent 0388161754
commit 8bea821f93
1 changed files with 1 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
artiq/coredevice/phaser.py
View File

@ -1071,12 +1071,7 @@ class PhaserChannel:
if (profile < 0) or (profile > 3):
raise ValueError("invalid profile index")
addr = PHASER_ADDR_SERVO_CFG0 + self.index
data = 0
if bypass == 0:
data = 1
if hold == 1:
data = data | (1 << 1)
data = data | (profile << 2)
data = (profile << 2) | ((hold & 1) << 1) | (~bypass & 1)
self.phaser.write8(addr, data)
@kernel