forked from M-Labs/artiq
runtime: refactor ttl*()
* remove rt2wb_output * remove ttl_*() ttl.c ttl.h * use rtio_output() and rtio_input_timestamp() * adapt coredevice/compiler layer * adapt bridge to not artiq_raise_from_c()
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@ -2,12 +2,6 @@ from artiq.language.core import *
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from artiq.language.types import *
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@syscall
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def rt2wb_output(time_mu: TInt64, channel: TInt32, addr: TInt32, data: TInt32
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) -> TNone:
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raise NotImplementedError("syscall not simulated")
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@syscall
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def rt2wb_input(channel: TInt32) -> TInt32:
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raise NotImplementedError("syscall not simulated")
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@ -0,0 +1,13 @@
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from artiq.language.core import syscall
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from artiq.language.types import TInt64, TInt32, TNone
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@syscall
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def rtio_output(time_mu: TInt64, channel: TInt32, addr: TInt32, data: TInt32
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) -> TNone:
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raise NotImplementedError("syscall not simulated")
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@syscall
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def rtio_input_timestamp(timeout_mu: TInt64, channel: TInt32) -> TInt64:
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raise NotImplementedError("syscall not simulated")
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@ -1,7 +1,8 @@
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from artiq.language.core import (kernel, seconds_to_mu, now_mu,
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delay_mu, int)
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from artiq.language.units import MHz
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from artiq.coredevice.rt2wb import rt2wb_output, rt2wb_input
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from artiq.coredevice.rtio import rtio_output as rt2wb_output
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from artiq.coredevice.rt2wb import rt2wb_input
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SPI_DATA_ADDR, SPI_XFER_ADDR, SPI_CONFIG_ADDR = range(3)
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@ -1,26 +1,6 @@
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from artiq.language.core import *
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from artiq.language.types import *
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@syscall
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def ttl_set_o(time_mu: TInt64, channel: TInt32, enabled: TBool) -> TNone:
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raise NotImplementedError("syscall not simulated")
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@syscall
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def ttl_set_oe(time_mu: TInt64, channel: TInt32, enabled: TBool) -> TNone:
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raise NotImplementedError("syscall not simulated")
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@syscall
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def ttl_set_sensitivity(time_mu: TInt64, channel: TInt32, sensitivity: TInt32) -> TNone:
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raise NotImplementedError("syscall not simulated")
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@syscall
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def ttl_get(channel: TInt32, time_limit_mu: TInt64) -> TInt64:
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raise NotImplementedError("syscall not simulated")
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@syscall
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def ttl_clock_set(time_mu: TInt64, channel: TInt32, ftw: TInt32) -> TNone:
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raise NotImplementedError("syscall not simulated")
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from artiq.coredevice.rtio import rtio_output, rtio_input_timestamp
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class TTLOut:
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@ -39,7 +19,7 @@ class TTLOut:
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@kernel
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def set_o(self, o):
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ttl_set_o(now_mu(), self.channel, o)
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rtio_output(now_mu(), self.channel, 0, 1 if o else 0)
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self.o_previous_timestamp = now_mu()
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@kernel
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@ -108,7 +88,7 @@ class TTLInOut:
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@kernel
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def set_oe(self, oe):
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ttl_set_oe(now_mu(), self.channel, oe)
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rtio_output(now_mu(), self.channel, 1, 1 if oe else 0)
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@kernel
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def output(self):
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@ -128,7 +108,7 @@ class TTLInOut:
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@kernel
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def set_o(self, o):
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ttl_set_o(now_mu(), self.channel, o)
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rtio_output(now_mu(), self.channel, 0, 1 if o else 0)
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self.o_previous_timestamp = now_mu()
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@kernel
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@ -170,7 +150,7 @@ class TTLInOut:
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@kernel
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def _set_sensitivity(self, value):
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ttl_set_sensitivity(now_mu(), self.channel, value)
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rtio_output(now_mu(), self.channel, 2, 1 if value else 0)
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self.i_previous_timestamp = now_mu()
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@kernel
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@ -226,7 +206,7 @@ class TTLInOut:
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"""Poll the RTIO input during all the previously programmed gate
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openings, and returns the number of registered events."""
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count = 0
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while ttl_get(self.channel, self.i_previous_timestamp) >= 0:
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while rtio_input_timestamp(self.i_previous_timestamp, self.channel) >= 0:
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count += 1
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return count
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@ -237,7 +217,7 @@ class TTLInOut:
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If the gate is permanently closed, returns a negative value.
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"""
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return ttl_get(self.channel, self.i_previous_timestamp)
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return rtio_input_timestamp(self.i_previous_timestamp, self.channel)
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class TTLClockGen:
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@ -288,7 +268,7 @@ class TTLClockGen:
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that are not powers of two cause jitter of one RTIO clock cycle at the
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output.
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"""
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ttl_clock_set(now_mu(), self.channel, frequency)
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rtio_output(now_mu(), self.channel, 0, frequency)
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self.previous_timestamp = now_mu()
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@kernel
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@ -7,7 +7,7 @@ OBJECTS := isr.o clock.o rtiocrg.o flash_storage.o mailbox.o \
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session.o log.o analyzer.o moninj.o net_server.o bridge_ctl.o \
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ksupport_data.o kloader.o test_mode.o main.o
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OBJECTS_KSUPPORT := ksupport.o artiq_personality.o mailbox.o \
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bridge.o rtio.o ttl.o rt2wb.o dds.o
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bridge.o rtio.o rt2wb.o dds.o
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CFLAGS += -I$(LIBALLOC_DIRECTORY) \
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-I$(MISOC_DIRECTORY)/software/include/dyld \
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@ -1,21 +1,25 @@
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#include "mailbox.h"
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#include "messages.h"
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#include "rtio.h"
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#include "ttl.h"
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#include "dds.h"
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#include "bridge.h"
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#define TIME_BUFFER (8000 << CONFIG_RTIO_FINE_TS_WIDTH)
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static void dds_write(int addr, int data)
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static void rtio_output_blind(int channel, int addr, int data)
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{
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rtio_chan_sel_write(CONFIG_RTIO_DDS_CHANNEL);
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rtio_chan_sel_write(channel);
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rtio_o_address_write(addr);
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rtio_o_data_write(data);
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rtio_o_timestamp_write(rtio_get_counter() + TIME_BUFFER);
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rtio_o_we_write(1);
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}
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static void dds_write(int addr, int data)
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{
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rtio_output_blind(CONFIG_RTIO_DDS_CHANNEL, addr, data);
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}
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static int dds_read(int addr)
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{
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int r;
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@ -54,7 +58,7 @@ void bridge_main(void)
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struct msg_brg_ttl_out *msg;
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msg = (struct msg_brg_ttl_out *)umsg;
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ttl_set_oe(rtio_get_counter() + TIME_BUFFER, msg->channel, msg->value);
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rtio_output_blind(msg->channel, 0, msg->value);
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mailbox_acknowledge();
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break;
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}
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@ -62,7 +66,7 @@ void bridge_main(void)
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struct msg_brg_ttl_out *msg;
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msg = (struct msg_brg_ttl_out *)umsg;
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ttl_set_o(rtio_get_counter() + TIME_BUFFER, msg->channel, msg->value);
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rtio_output_blind(msg->channel, 1, msg->value);
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mailbox_acknowledge();
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break;
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}
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@ -2,7 +2,7 @@
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#include <stdio.h>
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#include "artiq_personality.h"
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#include "rt2wb.h"
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#include "rtio.h"
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#include "log.h"
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#include "dds.h"
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@ -26,7 +26,7 @@
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#endif
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#define DDS_WRITE(addr, data) do { \
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rt2wb_output(now, CONFIG_RTIO_DDS_CHANNEL, addr, data); \
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rtio_output(now, CONFIG_RTIO_DDS_CHANNEL, addr, data); \
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now += DURATION_WRITE; \
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} while(0)
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@ -13,7 +13,6 @@
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#include "messages.h"
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#include "bridge.h"
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#include "artiq_personality.h"
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#include "ttl.h"
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#include "dds.h"
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#include "rtio.h"
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#include "rt2wb.h"
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@ -110,19 +109,14 @@ static const struct symbol runtime_exports[] = {
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/* direct syscalls */
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{"rtio_get_counter", &rtio_get_counter},
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{"rtio_log", &rtio_log},
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{"ttl_set_o", &ttl_set_o},
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{"ttl_set_oe", &ttl_set_oe},
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{"ttl_set_sensitivity", &ttl_set_sensitivity},
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{"ttl_get", &ttl_get},
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{"ttl_clock_set", &ttl_clock_set},
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{"rtio_output", &rtio_output},
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{"rtio_input_timestamp", &rtio_input_timestamp},
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{"dds_init", &dds_init},
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{"dds_batch_enter", &dds_batch_enter},
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{"dds_batch_exit", &dds_batch_exit},
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{"dds_set", &dds_set},
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{"rt2wb_output", &rt2wb_output},
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{"rt2wb_input", &rt2wb_input},
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{"cache_get", &cache_get},
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@ -5,13 +5,6 @@
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#include "rt2wb.h"
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void rt2wb_output(long long int timestamp, int channel, int addr,
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unsigned int data)
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{
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rtio_output(timestamp, channel, addr, data);
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}
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unsigned int rt2wb_input(int channel)
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{
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unsigned int data;
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@ -3,10 +3,7 @@
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#include "rtio.h"
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void rt2wb_output(long long int timestamp, int channel, int addr,
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unsigned int data);
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unsigned int rt2wb_input(int channel);
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unsigned int rt2wb_input_sync(long long int timeout, int channel);
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#endif /* __RT2WB_H */
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@ -56,8 +56,9 @@ void rtio_output(long long int timestamp, int channel, unsigned int addr,
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}
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int rtio_input_wait(long long int timeout, int channel)
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long long int rtio_input_timestamp(long long int timeout, int channel)
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{
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long long int r;
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int status;
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rtio_chan_sel_write(channel);
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}
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/* input FIFO is empty - keep waiting */
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}
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return status;
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if (status & RTIO_I_STATUS_OVERFLOW)
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artiq_raise_from_c("RTIOOverflow",
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"RTIO input overflow on channel {0}",
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channel, 0, 0);
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if (status & RTIO_I_STATUS_EMPTY)
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return -1;
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r = rtio_i_timestamp_read();
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rtio_i_re_write(1);
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return r;
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}
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@ -19,6 +19,6 @@ void rtio_log(long long int timestamp, const char *format, ...);
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void rtio_log_va(long long int timestamp, const char *format, va_list args);
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void rtio_output(long long int timestamp, int channel, unsigned int address,
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unsigned int data);
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int rtio_input_wait(long long int timeout, int channel);
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long long int rtio_input_timestamp(long long int timeout, int channel);
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#endif /* __RTIO_H */
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@ -1,42 +0,0 @@
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#include <generated/csr.h>
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#include "artiq_personality.h"
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#include "rtio.h"
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#include "ttl.h"
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void ttl_set_o(long long int timestamp, int channel, int value)
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{
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rtio_output(timestamp, channel, 0, value);
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}
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void ttl_set_oe(long long int timestamp, int channel, int oe)
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{
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rtio_output(timestamp, channel, 1, oe);
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}
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void ttl_set_sensitivity(long long int timestamp, int channel, int sensitivity)
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{
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rtio_output(timestamp, channel, 2, sensitivity);
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}
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long long int ttl_get(int channel, long long int time_limit)
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{
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long long int r;
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int status = rtio_input_wait(time_limit, channel);
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if (status & RTIO_I_STATUS_OVERFLOW)
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artiq_raise_from_c("RTIOOverflow",
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"RTIO input overflow on channel {0}",
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channel, 0, 0);
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if (status & RTIO_I_STATUS_EMPTY)
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return -1;
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r = rtio_i_timestamp_read();
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rtio_i_re_write(1);
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return r;
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}
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void ttl_clock_set(long long int timestamp, int channel, int ftw)
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{
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rtio_output(timestamp, channel, 0, ftw);
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}
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@ -1,10 +0,0 @@
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#ifndef __TTL_H
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#define __TTL_H
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void ttl_set_o(long long int timestamp, int channel, int value);
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void ttl_set_oe(long long int timestamp, int channel, int oe);
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void ttl_set_sensitivity(long long int timestamp, int channel, int sensitivity);
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long long int ttl_get(int channel, long long int time_limit);
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void ttl_clock_set(long long int timestamp, int channel, int ftw);
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#endif /* __TTL_H */
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