From 8aa88cfe7013e437662ad78e4844af640ec85b4b Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Tue, 7 Aug 2018 17:21:31 +0800
Subject: [PATCH] kasli_sawgmaster: add Urukul-Sayma example

---
 .../repository/sines_urukul_sayma.py          | 42 +++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 artiq/examples/kasli_sawgmaster/repository/sines_urukul_sayma.py

diff --git a/artiq/examples/kasli_sawgmaster/repository/sines_urukul_sayma.py b/artiq/examples/kasli_sawgmaster/repository/sines_urukul_sayma.py
new file mode 100644
index 000000000..2ba4bb21b
--- /dev/null
+++ b/artiq/examples/kasli_sawgmaster/repository/sines_urukul_sayma.py
@@ -0,0 +1,42 @@
+from artiq.experiment import *
+
+
+class SinesUrukulSayma(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.setattr_device("urukul0_cpld")
+        self.urukul_chs = [self.get_device("urukul0_ch" + str(i)) for i in range(4)]
+        self.sawgs = [self.get_device("sawg"+str(i)) for i in range(8)]
+
+    @kernel
+    def run(self):
+        # Note: when testing sync, do not reboot Urukul, as it is not
+        # synchronized to the FPGA (yet).
+        self.core.reset()
+        self.urukul0_cpld.init()
+        for urukul_ch in self.urukul_chs:
+            delay(1*ms)
+            urukul_ch.init()
+            urukul_ch.set(9*MHz)
+            urukul_ch.set_att(6.)
+            urukul_ch.sw.on()
+
+        while True:
+            print("waiting for DRTIO ready...")
+            while not self.core.get_drtio_link_status(0):
+                pass
+            print("OK")
+
+            self.core.reset()
+
+            for sawg in self.sawgs:
+                delay(1*ms)
+                sawg.reset()
+
+            for sawg in self.sawgs:
+                delay(1*ms)
+                sawg.amplitude1.set(.4)
+                sawg.frequency0.set(9*MHz)
+
+            while self.core.get_drtio_link_status(0):
+                pass