diff --git a/artiq/coredevice/ad9910.py b/artiq/coredevice/ad9910.py
index 59ca91855..c7e1b49a1 100644
--- a/artiq/coredevice/ad9910.py
+++ b/artiq/coredevice/ad9910.py
@@ -230,3 +230,13 @@ class AD9910:
         :param att: Attenuation in dB.
         """
         self.cpld.set_att(self.chip_select - 4, att)
+
+    @kernel
+    def cfg_sw(self, state):
+        """Set CPLD CFG RF switch state. The RF switch is controlled by the
+        logical or of the CPLD configuration shift register
+        RF switch bit and the SW TTL line (if used).
+
+        :param state: CPLD CFG RF switch bit
+        """
+        self.cpld.cfg_sw(self.chip_select - 4, state)
diff --git a/artiq/coredevice/ad9912.py b/artiq/coredevice/ad9912.py
index a74e98331..749fd5e00 100644
--- a/artiq/coredevice/ad9912.py
+++ b/artiq/coredevice/ad9912.py
@@ -182,3 +182,13 @@ class AD9912:
         """
         self.set_mu(self.frequency_to_ftw(frequency),
             self.turns_to_pow(phase))
+
+    @kernel
+    def cfg_sw(self, state):
+        """Set CPLD CFG RF switch state. The RF switch is controlled by the
+        logical or of the CPLD configuration shift register
+        RF switch bit and the SW TTL line (if used).
+
+        :param state: CPLD CFG RF switch bit
+        """
+        self.cpld.cfg_sw(self.chip_select - 4, state)
diff --git a/artiq/coredevice/urukul.py b/artiq/coredevice/urukul.py
index 7f844ee64..fe9c1a68c 100644
--- a/artiq/coredevice/urukul.py
+++ b/artiq/coredevice/urukul.py
@@ -231,6 +231,14 @@ class CPLD:
             c &= ~(1 << channel)
         self.cfg_write(c)
 
+    @kernel
+    def cfg_switches(self, state):
+        """Configure all four RF switches through the configuration register.
+
+        :param state: RF switch state as a 4 bit integer.
+        """
+        self.cfg_write((self.cfg_reg & ~0xf) | state)
+
     @kernel
     def set_att_mu(self, channel, att):
         """Set digital step attenuator in machine units.