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serwb: revert to 125MHz linerate (until we understand why 1gbps version breaks between builds)

This commit is contained in:
Florent Kermarrec 2018-06-07 15:13:56 +02:00
parent b4c2b148d1
commit 89797d08ed
2 changed files with 5 additions and 5 deletions
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2
artiq/gateware/targets/sayma_amc.py
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@ -200,7 +200,7 @@ class Standalone(MiniSoC, AMPSoC):
# AMC/RTM serwb # AMC/RTM serwb
serwb_pads = platform.request("amc_rtm_serwb") serwb_pads = platform.request("amc_rtm_serwb")
serwb_phy_amc = serwb.phy.SERWBPHY(platform.device, serwb_pads, mode="master") serwb_phy_amc = serwb.genphy.SERWBPHY(platform.device, serwb_pads, mode="master")
self.submodules.serwb_phy_amc = serwb_phy_amc self.submodules.serwb_phy_amc = serwb_phy_amc
self.csr_devices.append("serwb_phy_amc") self.csr_devices.append("serwb_phy_amc")

8
artiq/gateware/targets/sayma_rtm.py
View File

@ -42,8 +42,8 @@ class CRG(Module):
p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
# VCO @ 1GHz # VCO @ 1GHz
p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=10.0, p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=8.0,
p_CLKFBOUT_MULT_F=10, p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT_F=8, p_DIVCLK_DIVIDE=1,
i_CLKIN1=serwb_refclk_bufg, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, i_CLKIN1=serwb_refclk_bufg, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
# 500MHz # 500MHz
@ -181,8 +181,8 @@ class SaymaRTM(Module):
# AMC/RTM serwb # AMC/RTM serwb
serwb_pads = platform.request("amc_rtm_serwb") serwb_pads = platform.request("amc_rtm_serwb")
platform.add_period_constraint(serwb_pads.clk_p, 10.) platform.add_period_constraint(serwb_pads.clk_p, 8.)
serwb_phy_rtm = serwb.phy.SERWBPHY(platform.device, serwb_pads, mode="slave") serwb_phy_rtm = serwb.genphy.SERWBPHY(platform.device, serwb_pads, mode="slave")
self.submodules.serwb_phy_rtm = serwb_phy_rtm self.submodules.serwb_phy_rtm = serwb_phy_rtm
self.comb += [ self.comb += [
self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.clocking.refclk), self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.clocking.refclk),