From 89797d08ed3247d12b05880cb76739f4ba1d3769 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 7 Jun 2018 15:13:56 +0200 Subject: [PATCH] serwb: revert to 125MHz linerate (until we understand why 1gbps version breaks between builds) --- artiq/gateware/targets/sayma_amc.py | 2 +- artiq/gateware/targets/sayma_rtm.py | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index 0333a1c7f..b7aebf62f 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -200,7 +200,7 @@ class Standalone(MiniSoC, AMPSoC): # AMC/RTM serwb serwb_pads = platform.request("amc_rtm_serwb") - serwb_phy_amc = serwb.phy.SERWBPHY(platform.device, serwb_pads, mode="master") + serwb_phy_amc = serwb.genphy.SERWBPHY(platform.device, serwb_pads, mode="master") self.submodules.serwb_phy_amc = serwb_phy_amc self.csr_devices.append("serwb_phy_amc") diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py index faa290c28..ac376f5d2 100755 --- a/artiq/gateware/targets/sayma_rtm.py +++ b/artiq/gateware/targets/sayma_rtm.py @@ -42,8 +42,8 @@ class CRG(Module): p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked, # VCO @ 1GHz - p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=10.0, - p_CLKFBOUT_MULT_F=10, p_DIVCLK_DIVIDE=1, + p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=8.0, + p_CLKFBOUT_MULT_F=8, p_DIVCLK_DIVIDE=1, i_CLKIN1=serwb_refclk_bufg, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, # 500MHz @@ -181,8 +181,8 @@ class SaymaRTM(Module): # AMC/RTM serwb serwb_pads = platform.request("amc_rtm_serwb") - platform.add_period_constraint(serwb_pads.clk_p, 10.) - serwb_phy_rtm = serwb.phy.SERWBPHY(platform.device, serwb_pads, mode="slave") + platform.add_period_constraint(serwb_pads.clk_p, 8.) + serwb_phy_rtm = serwb.genphy.SERWBPHY(platform.device, serwb_pads, mode="slave") self.submodules.serwb_phy_rtm = serwb_phy_rtm self.comb += [ self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.clocking.refclk),