forked from M-Labs/artiq
drtio: separate aux controller
This helps with managing CSR groups and heterogeneous (satellite/repeaters) DRTIO cores.
This commit is contained in:
parent
92be9324df
commit
87e0384e97
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@ -2,7 +2,7 @@ use core::slice;
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use crc;
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use io::{ProtoRead, ProtoWrite, Cursor, Error as IoError};
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use board_misoc::{csr::DRTIO, mem::DRTIO_AUX, clock};
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use board_misoc::{csr::DRTIOAUX, mem::DRTIOAUX_MEM, clock};
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use proto_artiq::drtioaux_proto::Error as ProtocolError;
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pub use proto_artiq::drtioaux_proto::Packet;
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@ -40,17 +40,17 @@ pub fn reset(linkno: u8) {
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// clear buffer first to limit race window with buffer overflow
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// error. We assume the CPU is fast enough so that no two packets
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// will be received between the buffer and the error flag are cleared.
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(DRTIO[linkno].aux_rx_present_write)(1);
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(DRTIO[linkno].aux_rx_error_write)(1);
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(DRTIOAUX[linkno].aux_rx_present_write)(1);
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(DRTIOAUX[linkno].aux_rx_error_write)(1);
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}
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}
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fn has_rx_error(linkno: u8) -> bool {
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let linkno = linkno as usize;
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unsafe {
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let error = (DRTIO[linkno].aux_rx_error_read)() != 0;
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let error = (DRTIOAUX[linkno].aux_rx_error_read)() != 0;
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if error {
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(DRTIO[linkno].aux_rx_error_write)(1)
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(DRTIOAUX[linkno].aux_rx_error_write)(1)
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}
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error
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}
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@ -61,11 +61,11 @@ fn receive<F, T>(linkno: u8, f: F) -> Result<Option<T>, Error<!>>
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{
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let linkidx = linkno as usize;
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unsafe {
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if (DRTIO[linkidx].aux_rx_present_read)() == 1 {
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let ptr = DRTIO_AUX[linkidx].base + DRTIO_AUX[linkidx].size / 2;
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let len = (DRTIO[linkidx].aux_rx_length_read)();
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if (DRTIOAUX[linkidx].aux_rx_present_read)() == 1 {
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let ptr = DRTIOAUX_MEM[linkidx].base + DRTIOAUX_MEM[linkidx].size / 2;
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let len = (DRTIOAUX[linkidx].aux_rx_length_read)();
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let result = f(slice::from_raw_parts(ptr as *mut u8, len as usize));
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(DRTIO[linkidx].aux_rx_present_write)(1);
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(DRTIOAUX[linkidx].aux_rx_present_write)(1);
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Ok(Some(result?))
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} else {
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Ok(None)
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@ -114,12 +114,12 @@ fn transmit<F>(linkno: u8, f: F) -> Result<(), Error<!>>
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{
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let linkno = linkno as usize;
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unsafe {
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while (DRTIO[linkno].aux_tx_read)() != 0 {}
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let ptr = DRTIO_AUX[linkno].base;
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let len = DRTIO_AUX[linkno].size / 2;
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while (DRTIOAUX[linkno].aux_tx_read)() != 0 {}
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let ptr = DRTIOAUX_MEM[linkno].base;
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let len = DRTIOAUX_MEM[linkno].size / 2;
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let len = f(slice::from_raw_parts_mut(ptr as *mut u8, len))?;
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(DRTIO[linkno].aux_tx_length_write)(len as u16);
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(DRTIO[linkno].aux_tx_write)(1);
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(DRTIOAUX[linkno].aux_tx_length_write)(len as u16);
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(DRTIOAUX[linkno].aux_tx_write)(1);
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Ok(())
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}
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}
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@ -146,7 +146,7 @@ pub fn send_link(linkno: u8, packet: &Packet) -> Result<(), Error<!>> {
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// TODO: routing
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fn get_linkno(nodeno: u8) -> Result<u8, Error<!>> {
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if nodeno == 0 || nodeno as usize > DRTIO.len() {
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if nodeno == 0 || nodeno as usize > DRTIOAUX.len() {
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return Err(Error::NoRoute)
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}
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Ok(nodeno - 1)
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@ -16,21 +16,21 @@ use board_artiq::hmc830_7043;
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fn drtio_reset(reset: bool) {
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unsafe {
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(csr::DRTIO[0].reset_write)(if reset { 1 } else { 0 });
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csr::drtiosat::reset_write(if reset { 1 } else { 0 });
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}
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}
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fn drtio_reset_phy(reset: bool) {
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unsafe {
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(csr::DRTIO[0].reset_phy_write)(if reset { 1 } else { 0 });
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csr::drtiosat::reset_phy_write(if reset { 1 } else { 0 });
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}
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}
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fn drtio_tsc_loaded() -> bool {
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unsafe {
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let tsc_loaded = (csr::DRTIO[0].tsc_loaded_read)() == 1;
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let tsc_loaded = csr::drtiosat::tsc_loaded_read() == 1;
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if tsc_loaded {
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(csr::DRTIO[0].tsc_loaded_write)(1);
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csr::drtiosat::tsc_loaded_write(1);
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}
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tsc_loaded
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}
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@ -56,29 +56,29 @@ fn process_aux_packet(packet: drtioaux::Packet) -> Result<(), drtioaux::Error<!>
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drtioaux::Packet::RtioErrorRequest => {
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let errors;
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unsafe {
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errors = (csr::DRTIO[0].rtio_error_read)();
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errors = csr::drtiosat::rtio_error_read();
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}
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if errors & 1 != 0 {
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let channel;
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unsafe {
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channel = (csr::DRTIO[0].sequence_error_channel_read)();
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(csr::DRTIO[0].rtio_error_write)(1);
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channel = csr::drtiosat::sequence_error_channel_read();
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csr::drtiosat::rtio_error_write(1);
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}
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drtioaux::send_link(0,
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&drtioaux::Packet::RtioErrorSequenceErrorReply { channel })
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} else if errors & 2 != 0 {
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let channel;
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unsafe {
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channel = (csr::DRTIO[0].collision_channel_read)();
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(csr::DRTIO[0].rtio_error_write)(2);
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channel = csr::drtiosat::collision_channel_read();
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csr::drtiosat::rtio_error_write(2);
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}
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drtioaux::send_link(0,
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&drtioaux::Packet::RtioErrorCollisionReply { channel })
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} else if errors & 4 != 0 {
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let channel;
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unsafe {
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channel = (csr::DRTIO[0].busy_channel_read)();
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(csr::DRTIO[0].rtio_error_write)(4);
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channel = csr::drtiosat::busy_channel_read();
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csr::drtiosat::rtio_error_write(4);
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}
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drtioaux::send_link(0,
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&drtioaux::Packet::RtioErrorBusyReply { channel })
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@ -201,7 +201,7 @@ fn process_aux_packets() {
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fn process_errors() {
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let errors;
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unsafe {
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errors = (csr::DRTIO[0].protocol_error_read)();
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errors = csr::drtiosat::protocol_error_read();
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}
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if errors & 1 != 0 {
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error!("received packet of an unknown type");
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@ -217,9 +217,9 @@ fn process_errors() {
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let timestamp_event;
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let timestamp_counter;
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unsafe {
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channel = (csr::DRTIO[0].underflow_channel_read)();
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timestamp_event = (csr::DRTIO[0].underflow_timestamp_event_read)() as i64;
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timestamp_counter = (csr::DRTIO[0].underflow_timestamp_counter_read)() as i64;
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channel = csr::drtiosat::underflow_channel_read();
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timestamp_event = csr::drtiosat::underflow_timestamp_event_read() as i64;
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timestamp_counter = csr::drtiosat::underflow_timestamp_counter_read() as i64;
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}
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error!("write underflow, channel={}, timestamp={}, counter={}, slack={}",
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channel, timestamp_event, timestamp_counter, timestamp_event-timestamp_counter);
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@ -228,7 +228,7 @@ fn process_errors() {
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error!("write overflow");
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}
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unsafe {
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(csr::DRTIO[0].protocol_error_write)(errors);
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csr::drtiosat::protocol_error_write(errors);
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}
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}
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@ -247,7 +247,7 @@ const SI5324_SETTINGS: si5324::FrequencySettings
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fn drtio_link_rx_up() -> bool {
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unsafe {
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(csr::DRTIO[0].rx_up_read)() == 1
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csr::drtiosat::rx_up_read() == 1
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}
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}
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@ -1,2 +1,2 @@
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from artiq.gateware.drtio.core import SyncRTIO, DRTIOSatellite, DRTIOMaster, DRTIORepeater
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from artiq.gateware.drtio.aux_controller import DRTIOAuxController
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@ -211,7 +211,7 @@ class Receiver(Module, AutoCSR):
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# TODO: FullMemoryWE should be applied by migen.build
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@FullMemoryWE()
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class AuxController(Module):
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class DRTIOAuxController(Module):
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def __init__(self, link_layer):
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self.bus = wishbone.Interface()
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self.submodules.transmitter = Transmitter(link_layer, len(self.bus.dat_w))
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@ -8,7 +8,7 @@ from misoc.interconnect.csr import *
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from artiq.gateware.rtio import cri, rtlink
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from artiq.gateware.rtio.sed.core import *
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from artiq.gateware.rtio.input_collector import *
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from artiq.gateware.drtio import (link_layer, aux_controller,
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from artiq.gateware.drtio import (link_layer,
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rt_packet_satellite, rt_errors_satellite,
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rt_packet_master, rt_controller_master,
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rt_controller_repeater)
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@ -145,13 +145,10 @@ class DRTIOSatellite(Module):
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self.submodules.rt_errors = rt_errors_satellite.RTErrorsSatellite(
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self.rt_packet, tsc, self.cri, self.async_errors)
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self.submodules.aux_controller = aux_controller.AuxController(
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self.link_layer)
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def get_csrs(self):
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return ([self.reset, self.reset_phy, self.tsc_loaded] +
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self.link_layer.get_csrs() + self.link_stats.get_csrs() +
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self.rt_errors.get_csrs() + self.aux_controller.get_csrs())
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self.rt_errors.get_csrs())
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class DRTIOMaster(Module):
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tsc, self.rt_packet)
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self.submodules.rt_manager = rt_controller_master.RTManager(self.rt_packet)
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self.submodules.aux_controller = aux_controller.AuxController(
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self.link_layer)
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def get_csrs(self):
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return (self.link_layer.get_csrs() +
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self.link_stats.get_csrs() +
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self.rt_controller.get_csrs() +
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self.rt_manager.get_csrs() +
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self.aux_controller.get_csrs())
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self.rt_manager.get_csrs())
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@property
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def cri(self):
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@ -191,14 +184,10 @@ class DRTIORepeater(Module):
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self.submodules.rt_packet = rt_packet_repeater.RTPacketRepeater(tsc, self.link_layer)
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self.submodules.rt_controller = rt_controller_repeater.RTController(self.rt_packet)
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self.submodules.aux_controller = aux_controller.AuxController(
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self.link_layer)
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def get_csrs(self):
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return (self.link_layer.get_csrs() +
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self.link_stats.get_csrs() +
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self.rt_controller.get_csrs() +
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self.aux_controller.get_csrs())
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self.rt_controller.get_csrs())
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@property
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def cri(self):
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@ -21,7 +21,7 @@ from artiq.gateware import eem
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from artiq.gateware.drtio.transceiver import gtp_7series
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import DRTIOMaster, DRTIOSatellite, SyncRTIO
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from artiq.gateware.drtio import *
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from artiq.build_soc import *
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@ -622,7 +622,7 @@ class _MasterBase(MiniSoC, AMPSoC):
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"cri_con": 0x10000000,
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"rtio": 0x20000000,
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"rtio_dma": 0x30000000,
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"drtio_aux": 0x50000000,
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"drtioaux": 0x50000000,
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"mailbox": 0x70000000
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}
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mem_map.update(MiniSoC.mem_map)
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@ -666,27 +666,36 @@ class _MasterBase(MiniSoC, AMPSoC):
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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drtio_csr_group = []
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drtio_memory_group = []
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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self.drtio_cri = []
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for i in range(2):
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core_name = "drtio" + str(i)
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memory_name = "drtio" + str(i) + "_aux"
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coreaux_name = "drtioaux" + str(i)
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memory_name = "drtioaux" + str(i) + "_mem"
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drtio_csr_group.append(core_name)
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drtio_memory_group.append(memory_name)
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drtioaux_csr_group.append(coreaux_name)
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drtioaux_memory_group.append(memory_name)
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core = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})(
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DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i]))
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cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
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core = cdr(DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i]))
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setattr(self.submodules, core_name, core)
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self.drtio_cri.append(core.cri)
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self.csr_devices.append(core_name)
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memory_address = self.mem_map["drtio_aux"] + 0x800*i
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coreaux = cdr(DRTIOAuxController(core.link_layer))
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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memory_address = self.mem_map["drtioaux"] + 0x800*i
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self.add_wb_slave(memory_address, 0x800,
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core.aux_controller.bus)
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coreaux.bus)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.add_csr_group("drtio", drtio_csr_group)
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self.add_memory_group("drtio_aux", drtio_memory_group)
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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rtio_clk_period = 1e9/rtio_clk_freq
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gtp = self.drtio_transceiver.gtps[0]
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@ -759,7 +768,7 @@ class _MasterBase(MiniSoC, AMPSoC):
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class _SatelliteBase(BaseSoC):
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mem_map = {
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"drtio_aux": 0x50000000,
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"drtioaux": 0x50000000,
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}
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mem_map.update(BaseSoC.mem_map)
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@ -806,16 +815,19 @@ class _SatelliteBase(BaseSoC):
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rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
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self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer())
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self.submodules.drtio0 = rx0(DRTIOSatellite(
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self.submodules.drtiosat = rx0(DRTIOSatellite(
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self.rtio_tsc, self.drtio_transceiver.channels[0],
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self.rx_synchronizer))
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self.csr_devices.append("drtio0")
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self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
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self.drtio0.aux_controller.bus)
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self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
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self.csr_devices.append("drtiosat")
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self.submodules.drtioaux0 = rx0(DRTIOAuxController(
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self.drtiosat.link_layer))
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self.csr_devices.append("drtioaux0")
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self.add_wb_slave(self.mem_map["drtioaux"], 0x800,
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self.drtioaux0.bus)
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self.add_memory_region("drtioaux0_mem", self.mem_map["drtioaux"] | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.add_csr_group("drtio", ["drtio0"])
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self.add_memory_group("drtio_aux", ["drtio0_aux"])
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self.add_csr_group("drtioaux", ["drtioaux0"])
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self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"])
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.submodules.siphaser = SiPhaser7Series(
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@ -847,10 +859,10 @@ class _SatelliteBase(BaseSoC):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.drtio0_io = SyncRTIO(self.rtio_tsc, rtio_channels)
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self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
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self.comb += [
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self.drtio0.cri.connect(self.drtio0_io.cri),
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self.drtio0.async_errors.eq(self.drtio0_io.async_errors),
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self.drtiosat.cri.connect(self.local_io.cri),
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self.drtiosat.async_errors.eq(self.local_io.async_errors)
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]
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@ -22,7 +22,7 @@ from artiq.gateware.rtio.phy import ttl_simple, sawg
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from artiq.gateware.drtio.transceiver import gth_ultrascale
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import DRTIOMaster, DRTIOSatellite, SyncRTIO
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from artiq.gateware.drtio import *
|
||||
from artiq.build_soc import *
|
||||
|
||||
|
||||
|
@ -234,7 +234,7 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
|
|||
"rtio": 0x11000000,
|
||||
"rtio_dma": 0x12000000,
|
||||
"serwb": 0x13000000,
|
||||
"drtio_aux": 0x14000000,
|
||||
"drtioaux": 0x14000000,
|
||||
"mailbox": 0x70000000
|
||||
}
|
||||
mem_map.update(MiniSoC.mem_map)
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||||
|
@ -287,27 +287,36 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
|
|||
self.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
|
||||
|
||||
drtio_csr_group = []
|
||||
drtio_memory_group = []
|
||||
drtioaux_csr_group = []
|
||||
drtioaux_memory_group = []
|
||||
drtio_cri = []
|
||||
for i in range(2):
|
||||
core_name = "drtio" + str(i)
|
||||
memory_name = "drtio" + str(i) + "_aux"
|
||||
coreaux_name = "drtioaux" + str(i)
|
||||
memory_name = "drtioaux" + str(i) + "_mem"
|
||||
drtio_csr_group.append(core_name)
|
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drtio_memory_group.append(memory_name)
|
||||
drtioaux_csr_group.append(coreaux_name)
|
||||
drtioaux_memory_group.append(memory_name)
|
||||
|
||||
core = ClockDomainsRenamer({"rtio_rx": "rtio_rx"+str(i)})(
|
||||
DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i]))
|
||||
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
|
||||
|
||||
core = cdr(DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i]))
|
||||
setattr(self.submodules, core_name, core)
|
||||
drtio_cri.append(core.cri)
|
||||
self.csr_devices.append(core_name)
|
||||
|
||||
memory_address = self.mem_map["drtio_aux"] + 0x800*i
|
||||
coreaux = cdr(DRTIOAuxController(core.link_layer))
|
||||
setattr(self.submodules, coreaux_name, coreaux)
|
||||
self.csr_devices.append(coreaux_name)
|
||||
|
||||
memory_address = self.mem_map["drtioaux"] + 0x800*i
|
||||
self.add_wb_slave(memory_address, 0x800,
|
||||
core.aux_controller.bus)
|
||||
coreaux.bus)
|
||||
self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
|
||||
self.config["HAS_DRTIO"] = None
|
||||
self.add_csr_group("drtio", drtio_csr_group)
|
||||
self.add_memory_group("drtio_aux", drtio_memory_group)
|
||||
self.add_csr_group("drtioaux", drtioaux_csr_group)
|
||||
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
|
||||
|
||||
rtio_clk_period = 1e9/rtio_clk_freq
|
||||
gth = self.drtio_transceiver.gths[0]
|
||||
|
@ -389,7 +398,7 @@ class Master(MiniSoC, AMPSoC):
|
|||
"cri_con": 0x10000000,
|
||||
"rtio": 0x11000000,
|
||||
"rtio_dma": 0x12000000,
|
||||
"drtio_aux": 0x14000000,
|
||||
"drtioaux": 0x14000000,
|
||||
"mailbox": 0x70000000
|
||||
}
|
||||
mem_map.update(MiniSoC.mem_map)
|
||||
|
@ -433,27 +442,36 @@ class Master(MiniSoC, AMPSoC):
|
|||
self.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
|
||||
|
||||
drtio_csr_group = []
|
||||
drtio_memory_group = []
|
||||
drtioaux_csr_group = []
|
||||
drtioaux_memory_group = []
|
||||
drtio_cri = []
|
||||
for i in range(10):
|
||||
core_name = "drtio" + str(i)
|
||||
memory_name = "drtio" + str(i) + "_aux"
|
||||
coreaux_name = "drtioaux" + str(i)
|
||||
memory_name = "drtioaux" + str(i) + "_mem"
|
||||
drtio_csr_group.append(core_name)
|
||||
drtio_memory_group.append(memory_name)
|
||||
drtioaux_csr_group.append(coreaux_name)
|
||||
drtioaux_memory_group.append(memory_name)
|
||||
|
||||
core = ClockDomainsRenamer({"rtio_rx": "rtio_rx"+str(i)})(
|
||||
DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i]))
|
||||
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
|
||||
|
||||
core = cdr(DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i]))
|
||||
setattr(self.submodules, core_name, core)
|
||||
drtio_cri.append(core.cri)
|
||||
self.csr_devices.append(core_name)
|
||||
|
||||
memory_address = self.mem_map["drtio_aux"] + 0x800*i
|
||||
coreaux = cdr(DRTIOAuxController(core.link_layer))
|
||||
setattr(self.submodules, coreaux_name, coreaux)
|
||||
self.csr_devices.append(coreaux_name)
|
||||
|
||||
memory_address = self.mem_map["drtioaux"] + 0x800*i
|
||||
self.add_wb_slave(memory_address, 0x800,
|
||||
core.aux_controller.bus)
|
||||
coreaux.bus)
|
||||
self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
|
||||
self.config["HAS_DRTIO"] = None
|
||||
self.add_csr_group("drtio", drtio_csr_group)
|
||||
self.add_memory_group("drtio_aux", drtio_memory_group)
|
||||
self.add_csr_group("drtioaux", drtioaux_csr_group)
|
||||
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
|
||||
|
||||
rtio_clk_period = 1e9/rtio_clk_freq
|
||||
gth = self.drtio_transceiver.gths[0]
|
||||
|
@ -525,7 +543,7 @@ class Satellite(BaseSoC, RTMCommon):
|
|||
"""
|
||||
mem_map = {
|
||||
"serwb": 0x13000000,
|
||||
"drtio_aux": 0x14000000,
|
||||
"drtioaux": 0x14000000,
|
||||
}
|
||||
mem_map.update(BaseSoC.mem_map)
|
||||
|
||||
|
@ -592,21 +610,24 @@ class Satellite(BaseSoC, RTMCommon):
|
|||
|
||||
rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
|
||||
self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer())
|
||||
self.submodules.drtio0 = rx0(DRTIOSatellite(
|
||||
self.submodules.drtiosat = rx0(DRTIOSatellite(
|
||||
self.rtio_tsc, self.drtio_transceiver.channels[0],
|
||||
self.rx_synchronizer))
|
||||
self.csr_devices.append("drtio0")
|
||||
self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
|
||||
self.drtio0.aux_controller.bus)
|
||||
self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
|
||||
self.csr_devices.append("drtiosat")
|
||||
self.submodules.drtioaux0 = rx0(DRTIOAuxController(
|
||||
self.drtiosat.link_layer))
|
||||
self.csr_devices.append("drtioaux0")
|
||||
self.add_wb_slave(self.mem_map["drtioaux"], 0x800,
|
||||
self.drtioaux0.bus)
|
||||
self.add_memory_region("drtioaux0_mem", self.mem_map["drtioaux"] | self.shadow_base, 0x800)
|
||||
self.config["HAS_DRTIO"] = None
|
||||
self.add_csr_group("drtio", ["drtio0"])
|
||||
self.add_memory_group("drtio_aux", ["drtio0_aux"])
|
||||
self.add_csr_group("drtioaux", ["drtioaux0"])
|
||||
self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"])
|
||||
|
||||
self.submodules.drtio0_io = SyncRTIO(self.rtio_tsc, rtio_channels)
|
||||
self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
|
||||
self.comb += [
|
||||
self.drtio0.cri.connect(self.drtio0_io.cri),
|
||||
self.drtio0.async_errors.eq(self.drtio0_io.async_errors),
|
||||
self.drtiosat.cri.connect(self.local_io.cri),
|
||||
self.drtiosat.async_errors.eq(self.local_io.async_errors),
|
||||
]
|
||||
|
||||
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
|
||||
|
|
|
@ -36,7 +36,7 @@ class TB(Module):
|
|||
def __init__(self, nwords):
|
||||
self.submodules.link_layer = Loopback(nwords)
|
||||
self.submodules.aux_controller = ClockDomainsRenamer(
|
||||
{"rtio": "sys", "rtio_rx": "sys"})(AuxController(self.link_layer))
|
||||
{"rtio": "sys", "rtio_rx": "sys"})(DRTIOAuxController(self.link_layer))
|
||||
|
||||
|
||||
class TestAuxController(unittest.TestCase):
|
||||
|
|
Loading…
Reference in New Issue