forked from M-Labs/artiq
gateware: compress bitstreams
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parent
0bbe886669
commit
87dd09a71c
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@ -118,6 +118,12 @@ class _NIST_QCx(MiniSoC, AMPSoC):
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ident=artiq_version,
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ident=artiq_version,
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**kwargs)
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**kwargs)
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AMPSoC.__init__(self)
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AMPSoC.__init__(self)
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if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
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self.platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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])
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if isinstance(self.platform.toolchain, XilinxISEToolchain):
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self.platform.toolchain.bitgen_opt += " -g compress"
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self.submodules.leds = gpio.GPIOOut(Cat(
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self.submodules.leds = gpio.GPIOOut(Cat(
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self.platform.request("user_led", 0),
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self.platform.request("user_led", 0),
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@ -126,6 +126,7 @@ class NIST_QC1(BaseSoC, AMPSoC):
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platform = self.platform
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platform = self.platform
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platform.toolchain.bitgen_opt += " -g compress"
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platform.toolchain.ise_commands += """
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platform.toolchain.ise_commands += """
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trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd {build_name}.pcf
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trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd {build_name}.pcf
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"""
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"""
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