diff --git a/artiq/coredevice/shiftreg.py b/artiq/coredevice/shiftreg.py
index cf7b9466c..79000eba3 100644
--- a/artiq/coredevice/shiftreg.py
+++ b/artiq/coredevice/shiftreg.py
@@ -43,7 +43,8 @@ class ShiftReg:
         data = 0
         for i in range(self.n):
             data <<= 1
-            if self.ser_in.sample_input():
+            self.ser_in.sample_input()
+            if self.ser_in.sample_get():
                 data |= 1
             delay(self.dt)
             self.clk.on()