forked from M-Labs/artiq
gateware/targets/sayma_rtm: add false path between cd_sys and cd_clk200
This commit is contained in:
parent
8adb50037f
commit
86825a852c
|
@ -77,6 +77,10 @@ class SaymaRTM(Module):
|
|||
self.crg.cd_sys.clk.attr.add("keep")
|
||||
clk_freq = 125e6
|
||||
platform.add_period_constraint(self.crg.cd_sys.clk, 8.0)
|
||||
platform.add_period_constraint(self.crg.cd_clk200.clk, 5.0)
|
||||
platform.add_false_path_constraints(
|
||||
self.crg.cd_sys.clk,
|
||||
self.crg.cd_clk200.clk)
|
||||
|
||||
self.submodules.rtm_identifier = RTMIdentifier()
|
||||
csr_devices.append("rtm_identifier")
|
||||
|
|
Loading…
Reference in New Issue