forked from M-Labs/artiq
gateware/targets/sayma_rtm: add false path between cd_sys and cd_clk200
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8adb50037f
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86825a852c
@ -77,6 +77,10 @@ class SaymaRTM(Module):
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self.crg.cd_sys.clk.attr.add("keep")
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clk_freq = 125e6
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platform.add_period_constraint(self.crg.cd_sys.clk, 8.0)
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platform.add_period_constraint(self.crg.cd_clk200.clk, 5.0)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.crg.cd_clk200.clk)
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self.submodules.rtm_identifier = RTMIdentifier()
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csr_devices.append("rtm_identifier")
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