From 85bb64191715ada6fc6f4c8fe22a8cd5530637b9 Mon Sep 17 00:00:00 2001 From: hartytp Date: Tue, 6 Oct 2020 15:42:37 +0100 Subject: [PATCH] wrpll.ddmtd: fix first edge deglitcher The blind counter should be held in reset whenever the input is high, not just when there is a rising edge (otherwise the counter runs down during the main pulse and can then re-trigger on jitter from the falling edge) --- artiq/gateware/drtio/wrpll/ddmtd.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/gateware/drtio/wrpll/ddmtd.py b/artiq/gateware/drtio/wrpll/ddmtd.py index 5466d84e0..0ed3de69f 100644 --- a/artiq/gateware/drtio/wrpll/ddmtd.py +++ b/artiq/gateware/drtio/wrpll/ddmtd.py @@ -83,7 +83,7 @@ class DDMTDDeglitcherFirstEdge(Module): blind_counter = Signal(max=blind_period) self.sync.helper += [ If(blind_counter != 0, blind_counter.eq(blind_counter - 1)), - If(rising, blind_counter.eq(blind_period - 1)), + If(input_signal_r, blind_counter.eq(blind_period - 1)), self.detect.eq(rising & (blind_counter == 0)) ]