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drtio: integrate aux controller

This commit is contained in:
Sebastien Bourdeauducq 2016-11-14 17:20:47 +08:00
parent a4d92716da
commit 84bd962ed5
1 changed files with 12 additions and 2 deletions
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14
artiq/gateware/drtio/core.py
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@ -2,7 +2,7 @@ from types import SimpleNamespace
from migen import * from migen import *
from artiq.gateware.drtio import link_layer, rt_packets, iot, rt_controller from artiq.gateware.drtio import link_layer, rt_packets, iot, rt_controller, aux_controller
class DRTIOSatellite(Module): class DRTIOSatellite(Module):
@ -44,6 +44,12 @@ class DRTIOSatellite(Module):
self.cd_rio_phy.rst.eq(ResetSignal("rtio", allow_reset_less=True)), self.cd_rio_phy.rst.eq(ResetSignal("rtio", allow_reset_less=True)),
] ]
self.submodules.aux_controller = aux_controller.AuxController(
self.link_layer)
def get_csrs(self):
return self.aux_controller.get_csrs()
class DRTIOMaster(Module): class DRTIOMaster(Module):
def __init__(self, transceiver, channel_count=1024, fine_ts_width=3, ll_rx_ready_confirm=1000): def __init__(self, transceiver, channel_count=1024, fine_ts_width=3, ll_rx_ready_confirm=1000):
@ -58,10 +64,14 @@ class DRTIOMaster(Module):
self.rt_packets, channel_count, fine_ts_width) self.rt_packets, channel_count, fine_ts_width)
self.submodules.rt_manager = rt_controller.RTManager(self.rt_packets) self.submodules.rt_manager = rt_controller.RTManager(self.rt_packets)
self.submodules.aux_controller = aux_controller.AuxController(
self.link_layer)
def get_kernel_csrs(self): def get_kernel_csrs(self):
return self.rt_controller.get_kernel_csrs() return self.rt_controller.get_kernel_csrs()
def get_csrs(self): def get_csrs(self):
return (self.link_layer.get_csrs() + return (self.link_layer.get_csrs() +
self.rt_controller.get_csrs() + self.rt_controller.get_csrs() +
self.rt_manager.get_csrs()) self.rt_manager.get_csrs() +
self.aux_controller.get_csrs())