forked from M-Labs/artiq
compiler.testbench.embedding: allow compiling only.
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parent
7bcba52d6a
commit
844d37ff18
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@ -6,6 +6,12 @@ from artiq.master.worker_db import DeviceManager
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from artiq.coredevice.core import Core, CompileError
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from artiq.coredevice.core import Core, CompileError
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def main():
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def main():
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if len(sys.argv) > 1 and sys.argv[1] == "+compile":
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del sys.argv[1]
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compile_only = True
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else:
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compile_only = False
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with open(sys.argv[1]) as f:
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with open(sys.argv[1]) as f:
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testcase_code = compile(f.read(), f.name, "exec")
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testcase_code = compile(f.read(), f.name, "exec")
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testcase_vars = {'__name__': 'testbench'}
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testcase_vars = {'__name__': 'testbench'}
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@ -15,9 +21,12 @@ def main():
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try:
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try:
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core = Core(dmgr=DeviceManager(FlatFileDB(ddb_path)))
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core = Core(dmgr=DeviceManager(FlatFileDB(ddb_path)))
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core.run(testcase_vars["entrypoint"], (), {})
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if compile_only:
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print(core.comm.get_log())
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core.compile(testcase_vars["entrypoint"], (), {})
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core.comm.clear_log()
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else:
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core.run(testcase_vars["entrypoint"], (), {})
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print(core.comm.get_log())
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core.comm.clear_log()
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except CompileError as error:
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except CompileError as error:
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print("\n".join(error.__cause__.diagnostic.render(only_line=True)))
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print("\n".join(error.__cause__.diagnostic.render(only_line=True)))
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