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rtio/sed: pass sequence numbers through the FIFOs. Closes #978

This commit is contained in:
Sebastien Bourdeauducq 2018-05-02 10:57:57 +08:00
parent 05955bfd79
commit 83fb431cd0
1 changed files with 3 additions and 3 deletions
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6
artiq/gateware/rtio/sed/fifos.py
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@ -32,16 +32,16 @@ class FIFOs(Module):
fifos = [] fifos = []
for input, output in zip(self.input, self.output): for input, output in zip(self.input, self.output):
fifo = fifo_cls(layout_len(layout_payload), fifo_depth) fifo = fifo_cls(seqn_width + layout_len(layout_payload), fifo_depth)
self.submodules += fifo self.submodules += fifo
fifos.append(fifo) fifos.append(fifo)
self.comb += [ self.comb += [
fifo.din.eq(input.payload.raw_bits()), fifo.din.eq(Cat(input.seqn, input.payload.raw_bits())),
fifo.we.eq(input.we), fifo.we.eq(input.we),
input.writable.eq(fifo.writable), input.writable.eq(fifo.writable),
output.payload.raw_bits().eq(fifo.dout), Cat(output.seqn, output.payload.raw_bits()).eq(fifo.dout),
output.readable.eq(fifo.readable), output.readable.eq(fifo.readable),
fifo.re.eq(output.re) fifo.re.eq(output.re)
] ]