forked from M-Labs/artiq
drtio: remove outdated comment
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@ -156,7 +156,6 @@ class RTController(Module):
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timeout_counter = WaitTimer(8191)
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self.submodules += timeout_counter
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# TODO: collision, replace, busy
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cond_sequence_error = self.cri.timestamp < last_timestamps.dat_r
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cond_underflow = ((self.cri.timestamp[fine_ts_width:]
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- self.csrs.underflow_margin.storage[fine_ts_width:]) < self.counter.value_sys)
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