forked from M-Labs/artiq
drtio: fifo level -> fifo space
This commit is contained in:
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aa8e211735
commit
83bec06226
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@ -41,9 +41,9 @@ class IOT(Module):
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# FIFO level
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# FIFO level
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self.sync += \
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self.sync += \
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If(rt_packets.fifo_level_update &
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If(rt_packets.fifo_space_update &
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(rt_packets.fifo_level_channel == n),
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(rt_packets.fifo_space_channel == n),
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rt_packets.fifo_level.eq(fifo.level))
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rt_packets.fifo_space.eq(channel.ofifo_depth - fifo.level))
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# FIFO write
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# FIFO write
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self.comb += fifo.we.eq(rt_packets.write_stb)
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self.comb += fifo.we.eq(rt_packets.write_stb)
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@ -37,7 +37,7 @@ def get_m2s_layouts(alignment):
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("address", 16),
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("address", 16),
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("data_len", 8),
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("data_len", 8),
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("short_data", 8))
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("short_data", 8))
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plm.add_type("fifo_level_request", ("channel", 16))
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plm.add_type("fifo_space_request", ("channel", 16))
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return plm
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return plm
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@ -45,7 +45,7 @@ def get_s2m_layouts(alignment):
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plm = PacketLayoutManager(alignment)
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plm = PacketLayoutManager(alignment)
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plm.add_type("error", ("code", 8))
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plm.add_type("error", ("code", 8))
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plm.add_type("echo_reply")
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plm.add_type("echo_reply")
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plm.add_type("fifo_level_reply", ("level", 16))
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plm.add_type("fifo_space_reply", ("space", 16))
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return plm
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return plm
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@ -176,9 +176,9 @@ class RTPacketSatellite(Module):
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self.tsc_load = Signal()
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self.tsc_load = Signal()
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self.tsc_value = Signal(64)
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self.tsc_value = Signal(64)
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self.fifo_level_channel = Signal(16)
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self.fifo_space_channel = Signal(16)
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self.fifo_level_update = Signal()
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self.fifo_space_update = Signal()
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self.fifo_level = Signal(16)
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self.fifo_space = Signal(16)
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self.write_stb = Signal()
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self.write_stb = Signal()
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self.write_timestamp = Signal(64)
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self.write_timestamp = Signal(64)
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@ -210,14 +210,14 @@ class RTPacketSatellite(Module):
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err_set = Signal()
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err_set = Signal()
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err_req = Signal()
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err_req = Signal()
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err_ack = Signal()
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err_ack = Signal()
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fifo_level_set = Signal()
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fifo_space_set = Signal()
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fifo_level_req = Signal()
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fifo_space_req = Signal()
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fifo_level_ack = Signal()
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fifo_space_ack = Signal()
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self.sync += [
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self.sync += [
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If(err_ack, err_req.eq(0)),
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If(err_ack, err_req.eq(0)),
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If(err_set, err_req.eq(1)),
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If(err_set, err_req.eq(1)),
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If(fifo_level_ack, fifo_level_req.eq(0)),
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If(fifo_space_ack, fifo_space_req.eq(0)),
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If(fifo_level_set, fifo_level_req.eq(1)),
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If(fifo_space_set, fifo_space_req.eq(1)),
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]
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]
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err_code = Signal(max=len(error_codes)+1)
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err_code = Signal(max=len(error_codes)+1)
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@ -225,8 +225,8 @@ class RTPacketSatellite(Module):
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self.comb += [
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self.comb += [
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self.tsc_value.eq(
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self.tsc_value.eq(
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rx_dp.packet_as["set_time"].timestamp),
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rx_dp.packet_as["set_time"].timestamp),
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self.fifo_level_channel.eq(
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self.fifo_space_channel.eq(
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rx_dp.packet_as["fifo_level_request"].channel),
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rx_dp.packet_as["fifo_space_request"].channel),
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self.write_timestamp.eq(
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self.write_timestamp.eq(
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rx_dp.packet_as["write"].timestamp),
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rx_dp.packet_as["write"].timestamp),
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self.write_channel.eq(
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self.write_channel.eq(
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@ -250,8 +250,8 @@ class RTPacketSatellite(Module):
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rx_plm.types["echo_request"]: echo_req.eq(1),
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rx_plm.types["echo_request"]: echo_req.eq(1),
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rx_plm.types["set_time"]: NextState("SET_TIME"),
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rx_plm.types["set_time"]: NextState("SET_TIME"),
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rx_plm.types["write"]: NextState("WRITE"),
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rx_plm.types["write"]: NextState("WRITE"),
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rx_plm.types["fifo_level_request"]:
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rx_plm.types["fifo_space_request"]:
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NextState("FIFO_LEVEL"),
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NextState("FIFO_SPACE"),
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"default": [
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"default": [
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err_set.eq(1),
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err_set.eq(1),
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NextValue(err_code, error_codes["unknown_type"])]
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NextValue(err_code, error_codes["unknown_type"])]
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@ -267,9 +267,9 @@ class RTPacketSatellite(Module):
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self.write_stb.eq(1),
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self.write_stb.eq(1),
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NextState("INPUT")
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NextState("INPUT")
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)
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)
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rx_fsm.act("FIFO_LEVEL",
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rx_fsm.act("FIFO_SPACE",
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fifo_level_set.eq(1),
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fifo_space_set.eq(1),
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self.fifo_level_update.eq(1),
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self.fifo_space_update.eq(1),
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NextState("INPUT")
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NextState("INPUT")
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)
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)
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@ -279,7 +279,7 @@ class RTPacketSatellite(Module):
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tx_fsm.act("IDLE",
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tx_fsm.act("IDLE",
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If(echo_req, NextState("ECHO")),
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If(echo_req, NextState("ECHO")),
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If(fifo_level_req, NextState("FIFO_LEVEL")),
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If(fifo_space_req, NextState("FIFO_SPACE")),
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If(self.write_overflow, NextState("ERROR_WRITE_OVERFLOW")),
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If(self.write_overflow, NextState("ERROR_WRITE_OVERFLOW")),
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If(self.write_underflow, NextState("ERROR_WRITE_UNDERFLOW")),
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If(self.write_underflow, NextState("ERROR_WRITE_UNDERFLOW")),
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If(err_req, NextState("ERROR"))
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If(err_req, NextState("ERROR"))
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@ -289,9 +289,9 @@ class RTPacketSatellite(Module):
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tx_dp.stb.eq(1),
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tx_dp.stb.eq(1),
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If(tx_dp.done, NextState("IDLE"))
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If(tx_dp.done, NextState("IDLE"))
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)
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)
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tx_fsm.act("FIFO_LEVEL",
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tx_fsm.act("FIFO_SPACE",
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fifo_level_ack.eq(1),
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fifo_space_ack.eq(1),
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tx_dp.send("fifo_level_reply", level=self.fifo_level),
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tx_dp.send("fifo_space_reply", space=self.fifo_space),
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tx_dp.stb.eq(1),
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tx_dp.stb.eq(1),
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If(tx_dp.done, NextState("IDLE"))
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If(tx_dp.done, NextState("IDLE"))
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)
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)
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@ -378,12 +378,12 @@ class RTPacketMaster(Module):
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self.write_address = Signal(16)
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self.write_address = Signal(16)
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self.write_data = Signal(256)
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self.write_data = Signal(256)
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# fifo level interface
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# fifo space interface
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# write with timestamp[48:] == 0xffff to make a fifo level request
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# write with timestamp[48:] == 0xffff to make a fifo space request
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# (level requests have to be ordered wrt writes)
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# (space requests have to be ordered wrt writes)
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self.fifo_level_not = Signal()
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self.fifo_space_not = Signal()
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self.fifo_level_not_ack = Signal()
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self.fifo_space_not_ack = Signal()
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self.fifo_level = Signal(16)
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self.fifo_space = Signal(16)
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# echo interface
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# echo interface
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self.echo_stb = Signal()
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self.echo_stb = Signal()
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@ -394,7 +394,9 @@ class RTPacketMaster(Module):
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# set_time interface
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# set_time interface
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self.set_time_stb = Signal()
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self.set_time_stb = Signal()
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self.set_time_ack = Signal()
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self.set_time_ack = Signal()
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self.tsc_value = Signal(64) # in rtio domain, must be valid all time
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# in rtio domain, must be valid all time while there is
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# a set_time request pending
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self.tsc_value = Signal(64)
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# errors
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# errors
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self.error_not = Signal()
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self.error_not = Signal()
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@ -419,11 +421,11 @@ class RTPacketMaster(Module):
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write_address, write_data).eq(fifo.dout)
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write_address, write_data).eq(fifo.dout)
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]
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]
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fifo_level_not = Signal()
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fifo_space_not = Signal()
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fifo_level = Signal(16)
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fifo_space = Signal(16)
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self.submodules += _CrossDomainNotification("rtio_rx",
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self.submodules += _CrossDomainNotification("rtio_rx",
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fifo_level_not, fifo_level,
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fifo_space_not, fifo_space,
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self.fifo_level_not, self.fifo_level_not_ack, self.fifo_level)
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self.fifo_space_not, self.fifo_space_not_ack, self.fifo_space)
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set_time_stb = Signal()
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set_time_stb = Signal()
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set_time_ack = Signal()
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set_time_ack = Signal()
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@ -474,7 +476,7 @@ class RTPacketMaster(Module):
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short_data=write_data),
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short_data=write_data),
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If(wfifo.readable,
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If(wfifo.readable,
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If(write_timestamp[48:] == 0xffff,
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If(write_timestamp[48:] == 0xffff,
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NextState("FIFO_LEVEL")
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NextState("FIFO_SPACE")
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).Else(
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).Else(
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tx_dp.stb.eq(1),
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tx_dp.stb.eq(1),
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wfifo.re.eq(tx_dp.done)
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wfifo.re.eq(tx_dp.done)
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@ -489,8 +491,8 @@ class RTPacketMaster(Module):
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)
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)
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)
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)
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)
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)
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tx_fsm.act("FIFO_LEVEL",
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tx_fsm.act("FIFO_SPACE",
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tx_dp.send("fifo_level_request", channel=write_channel),
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tx_dp.send("fifo_space_request", channel=write_channel),
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tx_dp.stb.eq(1),
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tx_dp.stb.eq(1),
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If(tx_dp.done, NextState("IDLE_WRITE"))
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If(tx_dp.done, NextState("IDLE_WRITE"))
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)
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)
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@ -519,7 +521,7 @@ class RTPacketMaster(Module):
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Case(rx_dp.packet_type, {
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Case(rx_dp.packet_type, {
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rx_plm.types["error"]: NextState("ERROR"),
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rx_plm.types["error"]: NextState("ERROR"),
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rx_plm.types["echo_reply"]: echo_received_now.eq(1),
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rx_plm.types["echo_reply"]: echo_received_now.eq(1),
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rx_plm.types["fifo_level_reply"]: NextState("FIFO_LEVEL"),
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rx_plm.types["fifo_space_reply"]: NextState("FIFO_SPACE"),
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"default": [
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"default": [
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error_not.eq(1),
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error_not.eq(1),
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error_code.eq(error_codes["unknown_type"])
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error_code.eq(error_codes["unknown_type"])
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@ -533,8 +535,8 @@ class RTPacketMaster(Module):
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error_code.eq(rx_dp.packet_as["error"].code),
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error_code.eq(rx_dp.packet_as["error"].code),
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NextState("INPUT")
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NextState("INPUT")
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)
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)
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rx_fsm.act("FIFO_LEVEL",
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rx_fsm.act("FIFO_SPACE",
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fifo_level_not.eq(1),
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fifo_space_not.eq(1),
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fifo_level.eq(rx_dp.packet_as["fifo_level_reply"].level),
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fifo_space.eq(rx_dp.packet_as["fifo_space_reply"].space),
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NextState("INPUT")
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NextState("INPUT")
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)
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)
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