From 838127d914802eec5dec84ba5fed469ca9920b60 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Sun, 2 Jul 2017 10:24:01 +0800
Subject: [PATCH] rtio: break DMA timing path

---
 artiq/gateware/rtio/dma.py | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/artiq/gateware/rtio/dma.py b/artiq/gateware/rtio/dma.py
index 1c7c3946e..0168282b4 100644
--- a/artiq/gateware/rtio/dma.py
+++ b/artiq/gateware/rtio/dma.py
@@ -226,9 +226,9 @@ class TimeOffset(Module, AutoCSR):
 
         # # #
 
-        pipe_ce = Signal()
-        self.sync += \
-            If(pipe_ce,
+        self.sync += [
+            If(self.source.ack, self.source.stb.eq(0)),
+            If(~self.source.stb,
                 self.sink.payload.connect(self.source.payload,
                                           leave_out={"timestamp"}),
                 self.source.payload.timestamp.eq(self.sink.payload.timestamp
@@ -236,10 +236,8 @@ class TimeOffset(Module, AutoCSR):
                 self.source.eop.eq(self.sink.eop),
                 self.source.stb.eq(self.sink.stb)
             )
-        self.comb += [
-            pipe_ce.eq(self.source.ack | ~self.source.stb),
-            self.sink.ack.eq(pipe_ce)
         ]
+        self.comb += self.sink.ack.eq(~self.source.stb)
 
 
 class CRIMaster(Module, AutoCSR):