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serwb: add phy_width parameter to allow reducing linerate to 500Mbps or 250Mbps

This commit is contained in:
Florent Kermarrec 2018-04-16 22:44:03 +02:00
parent f96f597ecb
commit 825a2158ba
3 changed files with 80 additions and 18 deletions
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43
artiq/gateware/serwb/kusphy.py
View File

@ -12,7 +12,8 @@ def K(x, y):
@ResetInserter() @ResetInserter()
class KUSSerdes(Module): class KUSSerdes(Module):
def __init__(self, pads, mode="master"): def __init__(self, pads, mode="master", phy_width=8):
assert phy_width in [2, 4, 8]
if mode == "slave": if mode == "slave":
self.refclk = Signal() self.refclk = Signal()
@ -78,7 +79,7 @@ class KUSSerdes(Module):
# tx datapath # tx datapath
# tx_data -> encoders -> converter -> serdes # tx_data -> encoders -> converter -> serdes
self.submodules.tx_converter = tx_converter = stream.Converter(40, 8) self.submodules.tx_converter = tx_converter = stream.Converter(40, phy_width)
self.comb += [ self.comb += [
tx_converter.sink.stb.eq(1), tx_converter.sink.stb.eq(1),
self.tx_ce.eq(tx_converter.sink.ack), self.tx_ce.eq(tx_converter.sink.ack),
@ -105,6 +106,22 @@ class KUSSerdes(Module):
] ]
serdes_o = Signal() serdes_o = Signal()
serdes_d = Signal(8)
if phy_width == 2:
self.comb += [
serdes_d[0:4].eq(Replicate(tx_converter.source.data[0], 4)),
serdes_d[4:8].eq(Replicate(tx_converter.source.data[1], 4))
]
elif phy_width == 4:
self.comb += [
serdes_d[0:2].eq(Replicate(tx_converter.source.data[0], 2)),
serdes_d[2:4].eq(Replicate(tx_converter.source.data[1], 2)),
serdes_d[4:6].eq(Replicate(tx_converter.source.data[2], 2)),
serdes_d[6:8].eq(Replicate(tx_converter.source.data[3], 2))
]
else:
self.comb += serdes_d.eq(tx_converter.source.data)
self.specials += [ self.specials += [
Instance("OSERDESE3", Instance("OSERDESE3",
p_DATA_WIDTH=8, p_INIT=0, p_DATA_WIDTH=8, p_INIT=0,
@ -113,7 +130,7 @@ class KUSSerdes(Module):
o_OQ=serdes_o, o_OQ=serdes_o,
i_RST=ResetSignal("sys"), i_RST=ResetSignal("sys"),
i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal("sys"), i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal("sys"),
i_D=tx_converter.source.data i_D=serdes_d
), ),
Instance("OBUFDS", Instance("OBUFDS",
i_I=serdes_o, i_I=serdes_o,
@ -146,7 +163,7 @@ class KUSSerdes(Module):
# rx datapath # rx datapath
# serdes -> converter -> bitslip -> decoders -> rx_data # serdes -> converter -> bitslip -> decoders -> rx_data
self.submodules.rx_converter = rx_converter = stream.Converter(8, 40) self.submodules.rx_converter = rx_converter = stream.Converter(phy_width, 40)
self.comb += [ self.comb += [
self.rx_ce.eq(rx_converter.source.stb), self.rx_ce.eq(rx_converter.source.stb),
rx_converter.source.ack.eq(1) rx_converter.source.ack.eq(1)
@ -194,9 +211,23 @@ class KUSSerdes(Module):
) )
] ]
self.comb += rx_converter.sink.stb.eq(1)
if phy_width == 2:
self.comb += [
rx_converter.sink.data[0].eq(serdes_q[0]),
rx_converter.sink.data[1].eq(serdes_q[4])
]
elif phy_width == 4:
self.comb += [
rx_converter.sink.data[0].eq(serdes_q[0]),
rx_converter.sink.data[1].eq(serdes_q[2]),
rx_converter.sink.data[2].eq(serdes_q[4]),
rx_converter.sink.data[3].eq(serdes_q[6]),
]
else:
self.comb += rx_converter.sink.data.eq(serdes_q)
self.comb += [ self.comb += [
rx_converter.sink.stb.eq(1),
rx_converter.sink.data.eq(serdes_q),
rx_bitslip.value.eq(self.rx_bitslip_value), rx_bitslip.value.eq(self.rx_bitslip_value),
rx_bitslip.i.eq(rx_converter.source.data), rx_bitslip.i.eq(rx_converter.source.data),
decoders[0].input.eq(rx_bitslip.o[0:10]), decoders[0].input.eq(rx_bitslip.o[0:10]),

6
artiq/gateware/serwb/phy.py
View File

@ -317,14 +317,14 @@ class _SerdesControl(Module, AutoCSR):
class SERWBPHY(Module, AutoCSR): class SERWBPHY(Module, AutoCSR):
def __init__(self, device, pads, mode="master"): def __init__(self, device, pads, mode="master", phy_width=8):
assert mode in ["master", "slave"] assert mode in ["master", "slave"]
if device[:4] == "xcku": if device[:4] == "xcku":
taps = 512 taps = 512
self.submodules.serdes = KUSSerdes(pads, mode) self.submodules.serdes = KUSSerdes(pads, mode, phy_width)
elif device[:4] == "xc7a": elif device[:4] == "xc7a":
taps = 32 taps = 32
self.submodules.serdes = S7Serdes(pads, mode) self.submodules.serdes = S7Serdes(pads, mode, phy_width)
else: else:
raise NotImplementedError raise NotImplementedError
if mode == "master": if mode == "master":

49
artiq/gateware/serwb/s7phy.py
View File

@ -12,7 +12,8 @@ def K(x, y):
@ResetInserter() @ResetInserter()
class S7Serdes(Module): class S7Serdes(Module):
def __init__(self, pads, mode="master"): def __init__(self, pads, mode="master", phy_width=8):
assert phy_width in [2, 4, 8]
if mode == "slave": if mode == "slave":
self.refclk = Signal() self.refclk = Signal()
@ -81,7 +82,7 @@ class S7Serdes(Module):
# tx datapath # tx datapath
# tx_data -> encoders -> converter -> serdes # tx_data -> encoders -> converter -> serdes
self.submodules.tx_converter = tx_converter = stream.Converter(40, 8) self.submodules.tx_converter = tx_converter = stream.Converter(40, phy_width)
self.comb += [ self.comb += [
tx_converter.sink.stb.eq(1), tx_converter.sink.stb.eq(1),
self.tx_ce.eq(tx_converter.sink.ack), self.tx_ce.eq(tx_converter.sink.ack),
@ -108,6 +109,22 @@ class S7Serdes(Module):
] ]
serdes_o = Signal() serdes_o = Signal()
serdes_d = Signal(8)
if phy_width == 2:
self.comb += [
serdes_d[0:4].eq(Replicate(tx_converter.source.data[0], 4)),
serdes_d[4:8].eq(Replicate(tx_converter.source.data[1], 4))
]
elif phy_width == 4:
self.comb += [
serdes_d[0:2].eq(Replicate(tx_converter.source.data[0], 2)),
serdes_d[2:4].eq(Replicate(tx_converter.source.data[1], 2)),
serdes_d[4:6].eq(Replicate(tx_converter.source.data[2], 2)),
serdes_d[6:8].eq(Replicate(tx_converter.source.data[3], 2))
]
else:
self.comb += serdes_d.eq(tx_converter.source.data)
self.specials += [ self.specials += [
Instance("OSERDESE2", Instance("OSERDESE2",
p_DATA_WIDTH=8, p_TRISTATE_WIDTH=1, p_DATA_WIDTH=8, p_TRISTATE_WIDTH=1,
@ -118,10 +135,10 @@ class S7Serdes(Module):
i_OCE=1, i_OCE=1,
i_RST=ResetSignal("sys"), i_RST=ResetSignal("sys"),
i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal("sys"), i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal("sys"),
i_D1=tx_converter.source.data[0], i_D2=tx_converter.source.data[1], i_D1=serdes_d[0], i_D2=serdes_d[1],
i_D3=tx_converter.source.data[2], i_D4=tx_converter.source.data[3], i_D3=serdes_d[2], i_D4=serdes_d[3],
i_D5=tx_converter.source.data[4], i_D6=tx_converter.source.data[5], i_D5=serdes_d[4], i_D6=serdes_d[5],
i_D7=tx_converter.source.data[6], i_D8=tx_converter.source.data[7] i_D7=serdes_d[6], i_D8=serdes_d[7]
), ),
Instance("OBUFDS", Instance("OBUFDS",
i_I=serdes_o, i_I=serdes_o,
@ -154,7 +171,7 @@ class S7Serdes(Module):
# rx datapath # rx datapath
# serdes -> converter -> bitslip -> decoders -> rx_data # serdes -> converter -> bitslip -> decoders -> rx_data
self.submodules.rx_converter = rx_converter = stream.Converter(8, 40) self.submodules.rx_converter = rx_converter = stream.Converter(phy_width, 40)
self.comb += [ self.comb += [
self.rx_ce.eq(rx_converter.source.stb), self.rx_ce.eq(rx_converter.source.stb),
rx_converter.source.ack.eq(1) rx_converter.source.ack.eq(1)
@ -205,9 +222,23 @@ class S7Serdes(Module):
) )
] ]
self.comb += rx_converter.sink.stb.eq(1)
if phy_width == 2:
self.comb += [
rx_converter.sink.data[0].eq(serdes_q[3]),
rx_converter.sink.data[1].eq(serdes_q[7])
]
elif phy_width == 4:
self.comb += [
rx_converter.sink.data[0].eq(serdes_q[1]),
rx_converter.sink.data[1].eq(serdes_q[3]),
rx_converter.sink.data[2].eq(serdes_q[5]),
rx_converter.sink.data[3].eq(serdes_q[7]),
]
else:
self.comb += rx_converter.sink.data.eq(serdes_q)
self.comb += [ self.comb += [
rx_converter.sink.stb.eq(1),
rx_converter.sink.data.eq(serdes_q),
rx_bitslip.value.eq(self.rx_bitslip_value), rx_bitslip.value.eq(self.rx_bitslip_value),
rx_bitslip.i.eq(rx_converter.source.data), rx_bitslip.i.eq(rx_converter.source.data),
decoders[0].input.eq(rx_bitslip.o[0:10]), decoders[0].input.eq(rx_bitslip.o[0:10]),