forked from M-Labs/artiq
serwb: add phy_width parameter to allow reducing linerate to 500Mbps or 250Mbps
This commit is contained in:
Florent Kermarrec
parent
f96f597ecb
commit
825a2158ba
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@ -12,7 +12,8 @@ def K(x, y):
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@ResetInserter()
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class KUSSerdes(Module):
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def __init__(self, pads, mode="master"):
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def __init__(self, pads, mode="master", phy_width=8):
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assert phy_width in [2, 4, 8]
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if mode == "slave":
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self.refclk = Signal()
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@ -78,7 +79,7 @@ class KUSSerdes(Module):
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# tx datapath
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# tx_data -> encoders -> converter -> serdes
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self.submodules.tx_converter = tx_converter = stream.Converter(40, 8)
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self.submodules.tx_converter = tx_converter = stream.Converter(40, phy_width)
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self.comb += [
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tx_converter.sink.stb.eq(1),
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self.tx_ce.eq(tx_converter.sink.ack),
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@ -105,6 +106,22 @@ class KUSSerdes(Module):
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]
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serdes_o = Signal()
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serdes_d = Signal(8)
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if phy_width == 2:
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self.comb += [
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serdes_d[0:4].eq(Replicate(tx_converter.source.data[0], 4)),
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serdes_d[4:8].eq(Replicate(tx_converter.source.data[1], 4))
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]
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elif phy_width == 4:
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self.comb += [
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serdes_d[0:2].eq(Replicate(tx_converter.source.data[0], 2)),
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serdes_d[2:4].eq(Replicate(tx_converter.source.data[1], 2)),
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serdes_d[4:6].eq(Replicate(tx_converter.source.data[2], 2)),
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serdes_d[6:8].eq(Replicate(tx_converter.source.data[3], 2))
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]
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else:
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self.comb += serdes_d.eq(tx_converter.source.data)
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self.specials += [
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Instance("OSERDESE3",
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p_DATA_WIDTH=8, p_INIT=0,
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@ -113,7 +130,7 @@ class KUSSerdes(Module):
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o_OQ=serdes_o,
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i_RST=ResetSignal("sys"),
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i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal("sys"),
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i_D=tx_converter.source.data
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i_D=serdes_d
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),
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Instance("OBUFDS",
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i_I=serdes_o,
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@ -146,7 +163,7 @@ class KUSSerdes(Module):
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# rx datapath
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# serdes -> converter -> bitslip -> decoders -> rx_data
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self.submodules.rx_converter = rx_converter = stream.Converter(8, 40)
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self.submodules.rx_converter = rx_converter = stream.Converter(phy_width, 40)
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self.comb += [
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self.rx_ce.eq(rx_converter.source.stb),
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rx_converter.source.ack.eq(1)
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@ -194,9 +211,23 @@ class KUSSerdes(Module):
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)
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]
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self.comb += rx_converter.sink.stb.eq(1)
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if phy_width == 2:
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self.comb += [
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rx_converter.sink.data[0].eq(serdes_q[0]),
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rx_converter.sink.data[1].eq(serdes_q[4])
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]
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elif phy_width == 4:
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self.comb += [
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rx_converter.sink.data[0].eq(serdes_q[0]),
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rx_converter.sink.data[1].eq(serdes_q[2]),
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rx_converter.sink.data[2].eq(serdes_q[4]),
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rx_converter.sink.data[3].eq(serdes_q[6]),
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]
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else:
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self.comb += rx_converter.sink.data.eq(serdes_q)
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self.comb += [
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rx_converter.sink.stb.eq(1),
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rx_converter.sink.data.eq(serdes_q),
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rx_bitslip.value.eq(self.rx_bitslip_value),
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rx_bitslip.i.eq(rx_converter.source.data),
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decoders[0].input.eq(rx_bitslip.o[0:10]),
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@ -317,14 +317,14 @@ class _SerdesControl(Module, AutoCSR):
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class SERWBPHY(Module, AutoCSR):
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def __init__(self, device, pads, mode="master"):
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def __init__(self, device, pads, mode="master", phy_width=8):
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assert mode in ["master", "slave"]
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if device[:4] == "xcku":
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taps = 512
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self.submodules.serdes = KUSSerdes(pads, mode)
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self.submodules.serdes = KUSSerdes(pads, mode, phy_width)
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elif device[:4] == "xc7a":
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taps = 32
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self.submodules.serdes = S7Serdes(pads, mode)
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self.submodules.serdes = S7Serdes(pads, mode, phy_width)
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else:
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raise NotImplementedError
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if mode == "master":
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@ -12,7 +12,8 @@ def K(x, y):
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@ResetInserter()
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class S7Serdes(Module):
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def __init__(self, pads, mode="master"):
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def __init__(self, pads, mode="master", phy_width=8):
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assert phy_width in [2, 4, 8]
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if mode == "slave":
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self.refclk = Signal()
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@ -81,7 +82,7 @@ class S7Serdes(Module):
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# tx datapath
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# tx_data -> encoders -> converter -> serdes
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self.submodules.tx_converter = tx_converter = stream.Converter(40, 8)
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self.submodules.tx_converter = tx_converter = stream.Converter(40, phy_width)
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self.comb += [
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tx_converter.sink.stb.eq(1),
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self.tx_ce.eq(tx_converter.sink.ack),
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@ -108,6 +109,22 @@ class S7Serdes(Module):
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]
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serdes_o = Signal()
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serdes_d = Signal(8)
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if phy_width == 2:
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self.comb += [
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serdes_d[0:4].eq(Replicate(tx_converter.source.data[0], 4)),
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serdes_d[4:8].eq(Replicate(tx_converter.source.data[1], 4))
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]
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elif phy_width == 4:
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self.comb += [
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serdes_d[0:2].eq(Replicate(tx_converter.source.data[0], 2)),
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serdes_d[2:4].eq(Replicate(tx_converter.source.data[1], 2)),
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serdes_d[4:6].eq(Replicate(tx_converter.source.data[2], 2)),
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serdes_d[6:8].eq(Replicate(tx_converter.source.data[3], 2))
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]
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else:
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self.comb += serdes_d.eq(tx_converter.source.data)
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self.specials += [
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Instance("OSERDESE2",
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p_DATA_WIDTH=8, p_TRISTATE_WIDTH=1,
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@ -118,10 +135,10 @@ class S7Serdes(Module):
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i_OCE=1,
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i_RST=ResetSignal("sys"),
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i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal("sys"),
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i_D1=tx_converter.source.data[0], i_D2=tx_converter.source.data[1],
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i_D3=tx_converter.source.data[2], i_D4=tx_converter.source.data[3],
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i_D5=tx_converter.source.data[4], i_D6=tx_converter.source.data[5],
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i_D7=tx_converter.source.data[6], i_D8=tx_converter.source.data[7]
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i_D1=serdes_d[0], i_D2=serdes_d[1],
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i_D3=serdes_d[2], i_D4=serdes_d[3],
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i_D5=serdes_d[4], i_D6=serdes_d[5],
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i_D7=serdes_d[6], i_D8=serdes_d[7]
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),
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Instance("OBUFDS",
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i_I=serdes_o,
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@ -154,7 +171,7 @@ class S7Serdes(Module):
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# rx datapath
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# serdes -> converter -> bitslip -> decoders -> rx_data
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self.submodules.rx_converter = rx_converter = stream.Converter(8, 40)
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self.submodules.rx_converter = rx_converter = stream.Converter(phy_width, 40)
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self.comb += [
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self.rx_ce.eq(rx_converter.source.stb),
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rx_converter.source.ack.eq(1)
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@ -205,9 +222,23 @@ class S7Serdes(Module):
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)
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]
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self.comb += rx_converter.sink.stb.eq(1)
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if phy_width == 2:
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self.comb += [
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rx_converter.sink.data[0].eq(serdes_q[3]),
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rx_converter.sink.data[1].eq(serdes_q[7])
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]
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elif phy_width == 4:
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self.comb += [
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rx_converter.sink.data[0].eq(serdes_q[1]),
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rx_converter.sink.data[1].eq(serdes_q[3]),
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rx_converter.sink.data[2].eq(serdes_q[5]),
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rx_converter.sink.data[3].eq(serdes_q[7]),
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]
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else:
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self.comb += rx_converter.sink.data.eq(serdes_q)
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self.comb += [
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rx_converter.sink.stb.eq(1),
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rx_converter.sink.data.eq(serdes_q),
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rx_bitslip.value.eq(self.rx_bitslip_value),
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rx_bitslip.i.eq(rx_converter.source.data),
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decoders[0].input.eq(rx_bitslip.o[0:10]),
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