srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

drtio/gth: add probes on {tx,rx}_init.done

This commit is contained in:
Sebastien Bourdeauducq 2017-12-28 16:49:08 +08:00
parent c086149782
commit 8153cfa88f
1 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/gateware/drtio/transceiver/gth_ultrascale.py
View File

@ -175,7 +175,9 @@ class GTHSingle(Module):
self.submodules += [ self.submodules += [
add_probe_async("drtio_gth", "cpll_lock", cpll_lock), add_probe_async("drtio_gth", "cpll_lock", cpll_lock),
add_probe_async("drtio_gth", "txuserrdy", tx_init.Xxuserrdy), add_probe_async("drtio_gth", "txuserrdy", tx_init.Xxuserrdy),
add_probe_async("drtio_gth", "tx_init_done", tx_init.done),
add_probe_async("drtio_gth", "rxuserrdy", rx_init.Xxuserrdy), add_probe_async("drtio_gth", "rxuserrdy", rx_init.Xxuserrdy),
add_probe_async("drtio_gth", "rx_init_done", rx_init.done),
add_probe_buffer("drtio_gth", "txdata", txdata, clock_domain="rtio_tx"), add_probe_buffer("drtio_gth", "txdata", txdata, clock_domain="rtio_tx"),
add_probe_buffer("drtio_gth", "rxdata", rxdata, clock_domain="rtio_rx") add_probe_buffer("drtio_gth", "rxdata", rxdata, clock_domain="rtio_rx")
] ]