diff --git a/artiq/firmware/libboard_artiq/ad9154.rs b/artiq/firmware/libboard_artiq/ad9154.rs
index 65a130311..703438a22 100644
--- a/artiq/firmware/libboard_artiq/ad9154.rs
+++ b/artiq/firmware/libboard_artiq/ad9154.rs
@@ -757,7 +757,7 @@ fn init_dac(dacno: u8) -> Result<(), &'static str> {
     // Run the PRBS, STPL and SYSREF scan tests
     dac_prbs(dacno)?;
     dac_stpl(dacno, 4, 2)?;
-    let sysref_phase = 58;
+    let sysref_phase = 61;
     dac_sysref_scan(dacno, sysref_phase);
     // Set SYSREF phase and reconfigure the DAC
     dac_sysref_cfg(dacno, sysref_phase);
diff --git a/artiq/firmware/libboard_artiq/hmc830_7043.rs b/artiq/firmware/libboard_artiq/hmc830_7043.rs
index 6d6184e45..59a69ba90 100644
--- a/artiq/firmware/libboard_artiq/hmc830_7043.rs
+++ b/artiq/firmware/libboard_artiq/hmc830_7043.rs
@@ -318,12 +318,14 @@ pub mod hmc7043 {
          *  Digital delay resolution: 1/2 input clock cycle = 416ps for 1.2GHz
          *  16*25ps = 400ps: limit analog delay to 16 steps instead of 32.
          */
+        let analog_delay = (phase % 17) as u8;
+        let digital_delay = (phase / 17) as u8;
         if dacno == 0 {
-            write(0x00d5, (phase & 0xf) as u8);
-            write(0x00d6, ((phase >> 4) & 0x1f) as u8);
+            write(0x00d5, analog_delay);
+            write(0x00d6, digital_delay);
         } else if dacno == 1 {
-            write(0x00e9, (phase & 0xf) as u8);
-            write(0x00ea, ((phase >> 4) & 0x1f) as u8);
+            write(0x00e9, analog_delay);
+            write(0x00ea, digital_delay);
         } else {
             unimplemented!();
         }