forked from M-Labs/artiq
coredevice/ad9912: add [untested, wip]
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280392708d
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"""
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Driver for the AD9912 DDS.
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"""
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from artiq.language.core import kernel, delay_mu
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from artiq.language.units import ns, us
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from artiq.coredevice import spi
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_AD9912_SPI_CONFIG = (0*spi.SPI_OFFLINE | 0*spi.SPI_CS_POLARITY |
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0*spi.SPI_CLK_POLARITY | 0*spi.SPI_CLK_PHASE |
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0*spi.SPI_LSB_FIRST | 0*spi.SPI_HALF_DUPLEX)
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class AD9912:
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"""
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Support for the Analog devices AD9912 DDS
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:param spi_device: Name of the SPI bus this device is on.
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:param chip_select: Value to drive on the chip select lines
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during transactions.
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"""
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def __init__(self, dmgr, spi_device, chip_select):
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self.core = dmgr.get("core")
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self.bus = dmgr.get(spi_device)
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self.chip_select = chip_select
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@kernel
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def setup_bus(self, write_div=5, read_div=20):
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"""Configure the SPI bus and the SPI transaction parameters
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for this device. This method has to be called before any other method
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if the bus has been used to access a different device in the meantime.
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This method advances the timeline by the duration of two
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RTIO-to-Wishbone bus transactions.
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:param write_div: Write clock divider.
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:param read_div: Read clock divider.
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"""
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# write: 5*8ns >= 40ns = t_clk (typ clk rate)
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# read: 2*8*ns >= 25ns = t_dv (clk falling to miso valid) + RTT
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self.bus.set_config_mu(_AD9912_SPI_CONFIG, write_div, read_div)
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self.bus.set_xfer(self.chip_select, 24, 0)
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@kernel
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def write(self, data):
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"""Write 24 bits of data.
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This method advances the timeline by the duration of the SPI transfer
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and the required CS high time.
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"""
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self.bus.write(data << 8)
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delay_mu(self.bus.ref_period_mu) # get to 20ns min cs high
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@ -0,0 +1,384 @@
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# auto-generated, do not edit
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from artiq.language.core import portable
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from artiq.language.types import TInt32
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AD9912_SER_CONF = 0x000
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# default: 0x00, access: R/W
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@portable
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def AD9912_SDOACTIVE_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 0
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@portable
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def AD9912_SDOACTIVE_GET(x: TInt32) -> TInt32:
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return (x >> 0) & 0x1
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# default: 0x00, access: R/W
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@portable
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def AD9912_LSBFIRST_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 1
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@portable
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def AD9912_LSBFIRST_GET(x: TInt32) -> TInt32:
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return (x >> 1) & 0x1
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# default: 0x00, access: R/W
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@portable
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def AD9912_SOFTRESET_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 2
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@portable
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def AD9912_SOFTRESET_GET(x: TInt32) -> TInt32:
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return (x >> 2) & 0x1
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# default: 0x01, access: R/W
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@portable
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def AD9912_LONGINSN_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 3
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@portable
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def AD9912_LONGINSN_GET(x: TInt32) -> TInt32:
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return (x >> 3) & 0x1
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# default: 0x01, access: R/W
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@portable
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def AD9912_LONGINSN_M_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 4
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@portable
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def AD9912_LONGINSN_M_GET(x: TInt32) -> TInt32:
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return (x >> 4) & 0x1
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# default: 0x00, access: R/W
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@portable
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def AD9912_SOFTRESET_M_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 5
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@portable
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def AD9912_SOFTRESET_M_GET(x: TInt32) -> TInt32:
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return (x >> 5) & 0x1
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# default: 0x00, access: R/W
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@portable
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def AD9912_LSBFIRST_M_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 6
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@portable
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def AD9912_LSBFIRST_M_GET(x: TInt32) -> TInt32:
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return (x >> 6) & 0x1
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# default: 0x00, access: R/W
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@portable
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def AD9912_SDOACTIVE_M_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 7
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@portable
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def AD9912_SDOACTIVE_M_GET(x: TInt32) -> TInt32:
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return (x >> 7) & 0x1
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AD9912_PRODIDL = 0x002
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AD9912_PRODIDH = 0x003
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AD9912_SER_OPT1 = 0x004
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# default: 0x00, access: R/W
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@portable
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def AD9912_READ_BUF_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 0
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@portable
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def AD9912_READ_BUF_GET(x: TInt32) -> TInt32:
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return (x >> 0) & 0x1
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AD9912_SER_OPT2 = 0x005
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# default: 0x00, access: R/W
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@portable
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def AD9912_RED_UPDATE_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 0
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@portable
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def AD9912_RED_UPDATE_GET(x: TInt32) -> TInt32:
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return (x >> 0) & 0x1
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AD9912_PWRCNTRL1 = 0x010
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# default: 0x00, access: R/W
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@portable
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def AD9912_PD_DIGITAL_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 0
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@portable
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def AD9912_PD_DIGITAL_GET(x: TInt32) -> TInt32:
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return (x >> 0) & 0x1
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# default: 0x00, access: R/W
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@portable
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def AD9912_PD_FULL_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 1
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@portable
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def AD9912_PD_FULL_GET(x: TInt32) -> TInt32:
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return (x >> 1) & 0x1
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# default: 0x00, access: R/W
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@portable
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def AD9912_PD_SYSCLK_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 4
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@portable
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def AD9912_PD_SYSCLK_GET(x: TInt32) -> TInt32:
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return (x >> 4) & 0x1
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# default: 0x00, access: R/W
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@portable
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def AD9912_EN_DOUBLER_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 5
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@portable
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def AD9912_EN_DOUBLER_GET(x: TInt32) -> TInt32:
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return (x >> 5) & 0x1
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# default: 0x01, access: R/W
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@portable
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def AD9912_EN_CMOS_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 6
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@portable
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def AD9912_EN_CMOS_GET(x: TInt32) -> TInt32:
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return (x >> 6) & 0x1
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# default: 0x01, access: R/W
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@portable
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def AD9912_PD_HSTL_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 7
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@portable
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def AD9912_PD_HSTL_GET(x: TInt32) -> TInt32:
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return (x >> 7) & 0x1
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AD9912_PWRCNTRL2 = 0x012
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# default: 0x00, access: R/W
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@portable
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def AD9912_DDS_RESET_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 0
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@portable
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def AD9912_DDS_RESET_GET(x: TInt32) -> TInt32:
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return (x >> 0) & 0x1
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AD9912_PWRCNTRL3 = 0x013
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# default: 0x00, access: R/W
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@portable
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def AD9912_S_DIV_RESET_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 1
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@portable
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def AD9912_S_DIV_RESET_GET(x: TInt32) -> TInt32:
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return (x >> 1) & 0x1
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# default: 0x00, access: R/W
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@portable
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def AD9912_S_DIV2_RESET_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 3
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@portable
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def AD9912_S_DIV2_RESET_GET(x: TInt32) -> TInt32:
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return (x >> 3) & 0x1
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# default: 0x00, access: R/W
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@portable
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def AD9912_PD_FUND_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 7
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@portable
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def AD9912_PD_FUND_GET(x: TInt32) -> TInt32:
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return (x >> 7) & 0x1
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AD9912_N_DIV = 0x020
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AD9912_PLLCFG = 0x022
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# default: 0x00, access: R/W
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@portable
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def AD9912_PLL_ICP_SET(x: TInt32) -> TInt32:
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return (x & 0x3) << 0
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@portable
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def AD9912_PLL_ICP_GET(x: TInt32) -> TInt32:
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return (x >> 0) & 0x3
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# default: 0x01, access: R/W
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@portable
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def AD9912_VCO_RANGE_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 2
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@portable
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def AD9912_VCO_RANGE_GET(x: TInt32) -> TInt32:
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return (x >> 2) & 0x1
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# default: 0x00, access: R/W
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@portable
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def AD9912_PLL_REF2X_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 3
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@portable
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def AD9912_PLL_REF2X_GET(x: TInt32) -> TInt32:
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return (x >> 3) & 0x1
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# default: 0x00, access: R/W
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@portable
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def AD9912_VCO_AUTO_RANGE_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 7
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@portable
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def AD9912_VCO_AUTO_RANGE_GET(x: TInt32) -> TInt32:
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return (x >> 7) & 0x1
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AD9912_S_DIVL = 0x104
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AD9912_S_DIVH = 0x105
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AD9912_S_DIV_CFG = 0x106
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# default: 0x01, access: R/W
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@portable
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def AD9912_S_DIV2_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 0
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@portable
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def AD9912_S_DIV2_GET(x: TInt32) -> TInt32:
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return (x >> 0) & 0x1
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# default: 0x00, access: R/W
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@portable
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def AD9912_S_DIV_FALL_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 7
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@portable
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def AD9912_S_DIV_FALL_GET(x: TInt32) -> TInt32:
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return (x >> 7) & 0x1
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AD9912_FTW0 = 0x1a6
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AD9912_FTW1 = 0x1a7
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AD9912_FTW2 = 0x1a8
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AD9912_FTW3 = 0x1a9
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AD9912_FTW4 = 0x1aa
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AD9912_FTW5 = 0x1ab
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AD9912_POW0 = 0x1ac
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AD9912_POW1 = 0x1ad
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AD9912_HSTL = 0x200
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# default: 0x01, access: R/W
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@portable
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def AD9912_HSTL_CFG_SET(x: TInt32) -> TInt32:
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return (x & 0x3) << 0
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@portable
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def AD9912_HSTL_CFG_GET(x: TInt32) -> TInt32:
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return (x >> 0) & 0x3
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# default: 0x01, access: R/W
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@portable
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def AD9912_HSTL_OPOL_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 4
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@portable
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def AD9912_HSTL_OPOL_GET(x: TInt32) -> TInt32:
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return (x >> 4) & 0x1
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AD9912_CMOS = 0x201
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# default: 0x00, access: R/W
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@portable
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def AD9912_CMOS_MUX_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 0
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@portable
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def AD9912_CMOS_MUX_GET(x: TInt32) -> TInt32:
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return (x >> 0) & 0x1
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AD9912_FSC0 = 0x40b
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AD9912_FSC1 = 0x40c
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AD9912_HSR_A_CFG = 0x500
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# default: 0x00, access: R/W
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@portable
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def AD9912_HSR_A_HARMONIC_SET(x: TInt32) -> TInt32:
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return (x & 0xf) << 0
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@portable
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def AD9912_HSR_A_HARMONIC_GET(x: TInt32) -> TInt32:
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return (x >> 0) & 0xf
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# default: 0x00, access: R/W
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@portable
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def AD9912_HSR_A_MAG2X_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 6
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@portable
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def AD9912_HSR_A_MAG2X_GET(x: TInt32) -> TInt32:
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return (x >> 6) & 0x1
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# default: 0x00, access: R/W
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@portable
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def AD9912_HSR_A_EN_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 7
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@portable
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def AD9912_HSR_A_EN_GET(x: TInt32) -> TInt32:
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return (x >> 7) & 0x1
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AD9912_HSR_A_MAG = 0x501
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AD9912_HSR_A_POW0 = 0x503
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AD9912_HSR_A_POW1 = 0x504
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AD9912_HSR_B_CFG = 0x505
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# default: 0x00, access: R/W
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@portable
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def AD9912_HSR_B_HARMONIC_SET(x: TInt32) -> TInt32:
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return (x & 0xf) << 0
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@portable
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def AD9912_HSR_B_HARMONIC_GET(x: TInt32) -> TInt32:
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return (x >> 0) & 0xf
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# default: 0x00, access: R/W
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@portable
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def AD9912_HSR_B_MAG2X_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 6
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@portable
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def AD9912_HSR_B_MAG2X_GET(x: TInt32) -> TInt32:
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return (x >> 6) & 0x1
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# default: 0x00, access: R/W
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@portable
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def AD9912_HSR_B_EN_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 7
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@portable
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def AD9912_HSR_B_EN_GET(x: TInt32) -> TInt32:
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return (x >> 7) & 0x1
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AD9912_HSR_B_MAG = 0x506
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AD9912_HSR_B_POW0 = 0x508
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AD9912_HSR_B_POW1 = 0x509
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