forked from M-Labs/artiq
jesd204sync: work around HMC7043 poor behavior with combined delays
The HMC7043 outputs poorly controlled signals when adjusting two delays at once. This commit puts the DAC in one-shot SYSREF mode, and only triggers synchronizations when SYSREF is stable.
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7f0b2ff594
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@ -370,28 +370,7 @@ fn dac_setup(dacno: u8, linerate: u64) -> Result<(), &'static str> {
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write(ad9154_reg::LMFC_VAR_0, 0x0a); // receive buffer delay
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write(ad9154_reg::LMFC_VAR_1, 0x0a);
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write(ad9154_reg::SYNC_ERRWINDOW, 0); // +- 1/2 DAC clock
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write(ad9154_reg::SYNC_CONTROL,
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0x9*ad9154_reg::SYNCMODE | 0*ad9154_reg::SYNCENABLE |
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0*ad9154_reg::SYNCARM | 1*ad9154_reg::SYNCCLRSTKY |
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1*ad9154_reg::SYNCCLRLAST);
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write(ad9154_reg::SYNC_CONTROL,
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0x9*ad9154_reg::SYNCMODE | 1*ad9154_reg::SYNCENABLE |
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0*ad9154_reg::SYNCARM | 1*ad9154_reg::SYNCCLRSTKY |
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1*ad9154_reg::SYNCCLRLAST);
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write(ad9154_reg::SYNC_CONTROL,
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0x9*ad9154_reg::SYNCMODE | 1*ad9154_reg::SYNCENABLE |
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1*ad9154_reg::SYNCARM | 0*ad9154_reg::SYNCCLRSTKY |
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0*ad9154_reg::SYNCCLRLAST);
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clock::spin_us(1000); // ensure at least one sysref edge
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if read(ad9154_reg::SYNC_CONTROL) & ad9154_reg::SYNCARM != 0 {
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return Err("no sysref edge");
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}
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if read(ad9154_reg::SYNC_STATUS) & ad9154_reg::SYNC_LOCK == 0 {
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return Err("no sync lock");
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}
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if read(ad9154_reg::SYNC_STATUS) & ad9154_reg::SYNC_WLIM != 0 {
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return Err("sysref phase error");
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}
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write(ad9154_reg::XBAR_LN_0_1,
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0*ad9154_reg::LOGICAL_LANE0_SRC | 1*ad9154_reg::LOGICAL_LANE1_SRC);
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write(ad9154_reg::XBAR_LN_2_3,
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@ -687,12 +666,26 @@ fn dac_cfg_retry(dacno: u8) -> Result<(), &'static str> {
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}
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}
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pub fn dac_get_sync_error(dacno: u8) -> u16 {
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pub fn dac_sync(dacno: u8) -> Result<bool, &'static str> {
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spi_setup(dacno);
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let sync_error = ((read(ad9154_reg::SYNC_CURRERR_L) as u16) |
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((read(ad9154_reg::SYNC_CURRERR_H) as u16) << 8))
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& 0x1ff;
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sync_error
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write(ad9154_reg::SYNC_CONTROL,
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0x1*ad9154_reg::SYNCMODE | 1*ad9154_reg::SYNCENABLE |
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1*ad9154_reg::SYNCARM | 1*ad9154_reg::SYNCCLRSTKY);
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clock::spin_us(1000); // ensure at least one sysref edge
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let sync_status = read(ad9154_reg::SYNC_STATUS);
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if sync_status & ad9154_reg::SYNC_BUSY != 0 {
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return Err("sync logic busy");
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}
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if sync_status & ad9154_reg::SYNC_LOCK == 0 {
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return Err("no sync lock");
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}
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if sync_status & ad9154_reg::SYNC_TRIP == 0 {
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return Err("no sysref edge");
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}
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let realign_occured = sync_status & ad9154_reg::SYNC_ROTATE != 0;
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Ok(realign_occured)
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}
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fn init_dac(dacno: u8) -> Result<(), &'static str> {
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@ -1,4 +1,4 @@
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use board_misoc::{csr, clock, config};
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use board_misoc::{csr, config};
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use hmc830_7043::hmc7043;
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use ad9154;
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@ -147,14 +147,12 @@ fn sysref_cal_dac(dacno: u8) -> Result<u16, &'static str> {
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let dmax;
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hmc7043::sysref_offset_dac(dacno, d);
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clock::spin_us(10000);
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let sync_error_last = ad9154::dac_get_sync_error(dacno);
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ad9154::dac_sync(dacno)?;
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loop {
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hmc7043::sysref_offset_dac(dacno, d);
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clock::spin_us(10000);
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let sync_error = ad9154::dac_get_sync_error(dacno);
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if sync_error != sync_error_last {
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let realign_occured = ad9154::dac_sync(dacno)?;
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if realign_occured {
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dmin = d;
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break;
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}
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@ -165,16 +163,14 @@ fn sysref_cal_dac(dacno: u8) -> Result<u16, &'static str> {
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}
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}
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d += 5; // get away from jitter
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d += 17; // get away from jitter
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hmc7043::sysref_offset_dac(dacno, d);
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clock::spin_us(10000);
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let sync_error_last = ad9154::dac_get_sync_error(dacno);
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ad9154::dac_sync(dacno)?;
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loop {
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hmc7043::sysref_offset_dac(dacno, d);
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clock::spin_us(10000);
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let sync_error = ad9154::dac_get_sync_error(dacno);
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if sync_error != sync_error_last {
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let realign_occured = ad9154::dac_sync(dacno)?;
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if realign_occured {
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dmax = d;
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break;
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}
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@ -197,28 +193,22 @@ fn sysref_dac_align(dacno: u8, phase: u16) -> Result<(), &'static str> {
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info!("verifying SYSREF margins at DAC-{}...", dacno);
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hmc7043::sysref_offset_dac(dacno, phase);
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clock::spin_us(10000);
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let sync_error_last = ad9154::dac_get_sync_error(dacno);
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ad9154::dac_sync(dacno)?;
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for d in 0..128 {
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hmc7043::sysref_offset_dac(dacno, phase - d);
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clock::spin_us(10000);
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let sync_error = ad9154::dac_get_sync_error(dacno);
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if sync_error != sync_error_last {
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info!(" sync error-: {} -> {}", sync_error_last, sync_error);
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let realign_occured = ad9154::dac_sync(dacno)?;
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if realign_occured {
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margin_minus = Some(d);
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break;
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}
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}
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hmc7043::sysref_offset_dac(dacno, phase);
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clock::spin_us(10000);
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let sync_error_last = ad9154::dac_get_sync_error(dacno);
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ad9154::dac_sync(dacno)?;
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for d in 0..128 {
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hmc7043::sysref_offset_dac(dacno, phase + d);
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clock::spin_us(10000);
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let sync_error = ad9154::dac_get_sync_error(dacno);
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if sync_error != sync_error_last {
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info!(" sync error+: {} -> {}", sync_error_last, sync_error);
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let realign_occured = ad9154::dac_sync(dacno)?;
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if realign_occured {
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margin_plus = Some(d);
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break;
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}
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@ -235,8 +225,9 @@ fn sysref_dac_align(dacno: u8, phase: u16) -> Result<(), &'static str> {
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return Err("Unable to determine SYSREF margins at DAC");
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}
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// Leave SYSREF at the correct setting
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// Put SYSREF at the correct phase and sync DAC
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hmc7043::sysref_offset_dac(dacno, phase);
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ad9154::dac_sync(dacno)?;
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Ok(())
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}
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