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soc/ad9858: do not drive FUD by default

This commit is contained in:
Sebastien Bourdeauducq 2014-09-11 23:11:00 +08:00
parent 1b58e1510d
commit 7efc28ede1
1 changed files with 14 additions and 12 deletions
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20
soc/artiqlib/ad9858/__init__.py
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@ -33,7 +33,7 @@ class AD9858(Module):
Round-trip addr A setup (> RX, RD, D to Z), RD prop, D valid (< D Round-trip addr A setup (> RX, RD, D to Z), RD prop, D valid (< D
valid), D prop is ~15 + 10 + 20 + 10 = 55ns valid), D prop is ~15 + 10 + 20 + 10 = 55ns
""" """
def __init__(self, pads, bus=None): def __init__(self, pads, drive_fud=False, bus=None):
if bus is None: if bus is None:
bus = wishbone.Interface() bus = wishbone.Interface()
self.bus = bus self.bus = bus
@ -66,6 +66,7 @@ class AD9858(Module):
bus.dat_r.eq(dr) bus.dat_r.eq(dr)
) )
if drive_fud:
fud = Signal() fud = Signal()
self.sync += pads.fud_n.eq(~fud) self.sync += pads.fud_n.eq(~fud)
@ -84,7 +85,7 @@ class AD9858(Module):
If(bus.adr[0], If(bus.adr[0],
NextState("GPIO") NextState("GPIO")
).Else( ).Else(
NextState("FUD") NextState("FUD") if drive_fud else None
) )
).Else( ).Else(
If(bus.we, If(bus.we,
@ -144,12 +145,7 @@ class AD9858(Module):
bus.ack.eq(1), bus.ack.eq(1),
NextState("IDLE") NextState("IDLE")
) )
fsm.act("GPIO", if drive_fud:
bus.ack.eq(1),
bus_r_gpio.eq(1),
If(bus.we, gpio_load.eq(1)),
NextState("IDLE")
)
fsm.act("FUD", fsm.act("FUD",
# 4ns FUD setup to SYNCLK # 4ns FUD setup to SYNCLK
# 0ns FUD hold to SYNCLK # 0ns FUD hold to SYNCLK
@ -157,6 +153,12 @@ class AD9858(Module):
bus.ack.eq(1), bus.ack.eq(1),
NextState("IDLE") NextState("IDLE")
) )
fsm.act("GPIO",
bus.ack.eq(1),
bus_r_gpio.eq(1),
If(bus.we, gpio_load.eq(1)),
NextState("IDLE")
)
def _test_gen(): def _test_gen():
@ -191,7 +193,7 @@ class _TestPads:
class _TB(Module): class _TB(Module):
def __init__(self): def __init__(self):
pads = _TestPads() pads = _TestPads()
self.submodules.dut = AD9858(pads) self.submodules.dut = AD9858(pads, drive_fud=True)
self.submodules.initiator = wishbone.Initiator(_test_gen()) self.submodules.initiator = wishbone.Initiator(_test_gen())
self.submodules.interconnect = wishbone.InterconnectPointToPoint( self.submodules.interconnect = wishbone.InterconnectPointToPoint(
self.initiator.bus, self.dut.bus) self.initiator.bus, self.dut.bus)