srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

nist_clock: add SPIMasters to spi buses

This commit is contained in:
Robert Jördens 2016-02-29 22:19:39 +01:00
parent 7ab7f7d75d
commit 7ef21f03b9
1 changed files with 9 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
artiq/gateware/targets/kc705.py
View File

@ -250,18 +250,24 @@ class NIST_CLOCK(_NIST_Ions):
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
spi_pins = self.platform.request("ams101_dac", 0) ams101_dac = self.platform.request("ams101_dac", 0)
phy = ttl_simple.Output(spi_pins.ldac) phy = ttl_simple.Output(ams101_dac.ldac)
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels) self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
phy = spi.SPIMaster(spi_pins) phy = spi.SPIMaster(ams101_dac)
self.submodules += phy self.submodules += phy
self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels) self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.Channel.from_phy( rtio_channels.append(rtio.Channel.from_phy(
phy, ofifo_depth=4, ififo_depth=4)) phy, ofifo_depth=4, ififo_depth=4))
for i in range(3):
phy = spi.SPIMaster(self.platform.request("spi", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(
phy, ofifo_depth=128, ififo_depth=128))
phy = ttl_simple.ClockGen(platform.request("la32_p")) phy = ttl_simple.ClockGen(platform.request("la32_p"))
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))