forked from M-Labs/artiq
nist_clock: add SPIMasters to spi buses
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7ab7f7d75d
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7ef21f03b9
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@ -250,18 +250,24 @@ class NIST_CLOCK(_NIST_Ions):
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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spi_pins = self.platform.request("ams101_dac", 0)
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phy = ttl_simple.Output(spi_pins.ldac)
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ams101_dac = self.platform.request("ams101_dac", 0)
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phy = ttl_simple.Output(ams101_dac.ldac)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
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phy = spi.SPIMaster(spi_pins)
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phy = spi.SPIMaster(ams101_dac)
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self.submodules += phy
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self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=4, ififo_depth=4))
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for i in range(3):
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phy = spi.SPIMaster(self.platform.request("spi", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=128, ififo_depth=128))
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phy = ttl_simple.ClockGen(platform.request("la32_p"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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