forked from M-Labs/artiq
test/coredevice/analyzer: test TTL input mode
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@ -1,16 +1,23 @@
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from artiq.language import *
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from artiq.language import *
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from artiq.coredevice.analyzer import decode_dump, OutputMessage
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from artiq.coredevice.analyzer import decode_dump, OutputMessage, InputMessage
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from artiq.test.hardware_testbench import ExperimentCase
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from artiq.test.hardware_testbench import ExperimentCase
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class CreateTTLPulse(EnvExperiment):
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class CreateTTLPulse(EnvExperiment):
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def build(self):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("core")
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self.setattr_device("ttl_out")
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self.setattr_device("ttl_inout")
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@kernel
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@kernel
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def run(self):
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def run(self):
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self.ttl_out.pulse_mu(1000)
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self.ttl_inout.output()
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delay_mu(100)
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with parallel:
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self.ttl_inout.gate_both_mu(1200)
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with sequential:
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delay_mu(100)
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self.ttl_inout.pulse_mu(1000)
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self.ttl_inout.count()
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class AnalyzerTest(ExperimentCase):
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class AnalyzerTest(ExperimentCase):
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@ -24,9 +31,16 @@ class AnalyzerTest(ExperimentCase):
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exp.run()
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exp.run()
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dump = decode_dump(comm.get_analyzer_dump())
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dump = decode_dump(comm.get_analyzer_dump())
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ttl_messages = [msg for msg in dump.messages
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output_messages = [msg for msg in dump.messages
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if isinstance(msg, OutputMessage)]
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if isinstance(msg, OutputMessage)
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self.assertEqual(len(ttl_messages), 2)
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and msg.address == 0]
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self.assertEqual(len(output_messages), 2)
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self.assertEqual(
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self.assertEqual(
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abs(ttl_messages[0].timestamp - ttl_messages[1].timestamp),
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abs(output_messages[0].timestamp - output_messages[1].timestamp),
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1000)
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1000)
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input_messages = [msg for msg in dump.messages
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if isinstance(msg, InputMessage)]
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self.assertEqual(len(input_messages), 2)
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self.assertAlmostEqual(
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abs(input_messages[0].timestamp - input_messages[1].timestamp),
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1000, delta=1)
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