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test/coredevice/analyzer: test TTL input mode

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This commit is contained in:
Sebastien Bourdeauducq 2015-12-26 21:10:19 +08:00
parent 82ec76af3e
commit 7eb4067477
1 changed files with 21 additions and 7 deletions
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28
artiq/test/coredevice/analyzer.py
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@ -1,16 +1,23 @@
from artiq.language import *
from artiq.coredevice.analyzer import decode_dump, OutputMessage
from artiq.coredevice.analyzer import decode_dump, OutputMessage, InputMessage
from artiq.test.hardware_testbench import ExperimentCase
class CreateTTLPulse(EnvExperiment):
def build(self):
self.setattr_device("core")
self.setattr_device("ttl_out")
self.setattr_device("ttl_inout")
@kernel
def run(self):
self.ttl_out.pulse_mu(1000)
self.ttl_inout.output()
delay_mu(100)
with parallel:
self.ttl_inout.gate_both_mu(1200)
with sequential:
delay_mu(100)
self.ttl_inout.pulse_mu(1000)
self.ttl_inout.count()
class AnalyzerTest(ExperimentCase):
@ -24,9 +31,16 @@ class AnalyzerTest(ExperimentCase):
exp.run()
dump = decode_dump(comm.get_analyzer_dump())
ttl_messages = [msg for msg in dump.messages
if isinstance(msg, OutputMessage)]
self.assertEqual(len(ttl_messages), 2)
output_messages = [msg for msg in dump.messages
if isinstance(msg, OutputMessage)
and msg.address == 0]
self.assertEqual(len(output_messages), 2)
self.assertEqual(
abs(ttl_messages[0].timestamp - ttl_messages[1].timestamp),
abs(output_messages[0].timestamp - output_messages[1].timestamp),
1000)
input_messages = [msg for msg in dump.messages
if isinstance(msg, InputMessage)]
self.assertEqual(len(input_messages), 2)
self.assertAlmostEqual(
abs(input_messages[0].timestamp - input_messages[1].timestamp),
1000, delta=1)