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targets: use _Peripherals/UP/AMP class names, share QC1 IO defs

This commit is contained in:
Sebastien Bourdeauducq 2015-04-07 00:07:53 +08:00
parent 1ed60e0829
commit 7e591bb1c7
4 changed files with 106 additions and 138 deletions
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82
artiq/gateware/nist_qc1.py Normal file
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@ -0,0 +1,82 @@
from mibuild.generic_platform import *
papilio_adapter_io = [
("ext_led", 0, Pins("B:7"), IOStandard("LVTTL")),
("pmt", 0, Pins("C:13"), IOStandard("LVTTL")),
("pmt", 1, Pins("C:14"), IOStandard("LVTTL")),
("xtrig", 0, Pins("C:12"), IOStandard("LVTTL")),
("dds_clock", 0, Pins("C:15"), IOStandard("LVTTL")), # PMT2
("ttl", 0, Pins("C:11"), IOStandard("LVTTL")),
("ttl", 1, Pins("C:10"), IOStandard("LVTTL")),
("ttl", 2, Pins("C:9"), IOStandard("LVTTL")),
("ttl", 3, Pins("C:8"), IOStandard("LVTTL")),
("ttl", 4, Pins("C:7"), IOStandard("LVTTL")),
("ttl", 5, Pins("C:6"), IOStandard("LVTTL")),
("ttl", 6, Pins("C:5"), IOStandard("LVTTL")),
("ttl", 7, Pins("C:4"), IOStandard("LVTTL")),
("ttl_l_tx_en", 0, Pins("A:9"), IOStandard("LVTTL")),
("ttl", 8, Pins("C:3"), IOStandard("LVTTL")),
("ttl", 9, Pins("C:2"), IOStandard("LVTTL")),
("ttl", 10, Pins("C:1"), IOStandard("LVTTL")),
("ttl", 11, Pins("C:0"), IOStandard("LVTTL")),
("ttl", 12, Pins("B:4"), IOStandard("LVTTL")),
("ttl", 13, Pins("A:11"), IOStandard("LVTTL")),
("ttl", 14, Pins("B:5"), IOStandard("LVTTL")),
("ttl", 15, Pins("A:10"), IOStandard("LVTTL")),
("ttl_h_tx_en", 0, Pins("B:6"), IOStandard("LVTTL")),
("dds", 0,
Subsignal("a", Pins("A:5 B:10 A:6 B:9 A:7 B:8")),
Subsignal("d", Pins("A:12 B:3 A:13 B:2 A:14 B:1 A:15 B:0")),
Subsignal("sel", Pins("A:2 B:14 A:1 B:15 A:0")),
Subsignal("p", Pins("A:8 B:12")),
Subsignal("fud_n", Pins("B:11")),
Subsignal("wr_n", Pins("A:4")),
Subsignal("rd_n", Pins("B:13")),
Subsignal("rst_n", Pins("A:3")),
IOStandard("LVTTL")),
]
fmc_adapter_io = [
("pmt", 0, Pins("LPC:LA20_N"), IOStandard("LVTTL")),
("pmt", 1, Pins("LPC:LA24_P"), IOStandard("LVTTL")),
("ttl", 0, Pins("LPC:LA21_P"), IOStandard("LVTTL")),
("ttl", 1, Pins("LPC:LA25_P"), IOStandard("LVTTL")),
("ttl", 2, Pins("LPC:LA21_N"), IOStandard("LVTTL")),
("ttl", 3, Pins("LPC:LA25_N"), IOStandard("LVTTL")),
("ttl", 4, Pins("LPC:LA22_P"), IOStandard("LVTTL")),
("ttl", 5, Pins("LPC:LA26_P"), IOStandard("LVTTL")),
("ttl", 6, Pins("LPC:LA22_N"), IOStandard("LVTTL")),
("ttl", 7, Pins("LPC:LA26_N"), IOStandard("LVTTL")),
("ttl", 8, Pins("LPC:LA23_P"), IOStandard("LVTTL")),
("ttl", 9, Pins("LPC:LA27_P"), IOStandard("LVTTL")),
("ttl", 10, Pins("LPC:LA23_N"), IOStandard("LVTTL")),
("ttl", 11, Pins("LPC:LA27_N"), IOStandard("LVTTL")),
("ttl", 12, Pins("LPC:LA00_CC_P"), IOStandard("LVTTL")),
("ttl", 13, Pins("LPC:LA10_P"), IOStandard("LVTTL")),
("ttl", 14, Pins("LPC:LA00_CC_N"), IOStandard("LVTTL")),
("ttl", 15, Pins("LPC:LA10_N"), IOStandard("LVTTL")),
("ttl_l_tx_en", 0, Pins("LPC:LA11_P"), IOStandard("LVTTL")),
("ttl_h_tx_en", 0, Pins("LPC:LA01_CC_P"), IOStandard("LVTTL")),
("dds", 0,
Subsignal("a", Pins("LPC:LA04_N LPC:LA14_N LPC:LA05_P LPC:LA15_P "
"LPC:LA05_N LPC:LA15_N")),
Subsignal("d", Pins("LPC:LA06_P LPC:LA16_P LPC:LA06_N LPC:LA16_N "
"LPC:LA07_P LPC:LA17_CC_P LPC:LA07_N "
"LPC:LA17_CC_N")),
Subsignal("sel", Pins("LPC:LA12_N LPC:LA03_P LPC:LA13_P LPC:LA03_N "
"LPC:LA13_N")),
Subsignal("p", Pins("LPC:LA11_N LPC:LA02_P")),
Subsignal("fud_n", Pins("LPC:LA14_P")),
Subsignal("wr_n", Pins("LPC:LA04_P")),
Subsignal("rd_n", Pins("LPC:LA02_N")),
Subsignal("rst_n", Pins("LPC:LA12_P")),
IOStandard("LVTTL")),
]

58
soc/targets/artiq_kc705.py
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@ -7,47 +7,7 @@ from misoclib.com import gpio
from misoclib.soc import mem_decoder from misoclib.soc import mem_decoder
from targets.kc705 import BaseSoC from targets.kc705 import BaseSoC
from artiq.gateware import amp, rtio, ad9858 from artiq.gateware import amp, rtio, ad9858, nist_qc1
_tester_io = [
("pmt", 0, Pins("LPC:LA20_N"), IOStandard("LVTTL")),
("pmt", 1, Pins("LPC:LA24_P"), IOStandard("LVTTL")),
("ttl", 0, Pins("LPC:LA21_P"), IOStandard("LVTTL")),
("ttl", 1, Pins("LPC:LA25_P"), IOStandard("LVTTL")),
("ttl", 2, Pins("LPC:LA21_N"), IOStandard("LVTTL")),
("ttl", 3, Pins("LPC:LA25_N"), IOStandard("LVTTL")),
("ttl", 4, Pins("LPC:LA22_P"), IOStandard("LVTTL")),
("ttl", 5, Pins("LPC:LA26_P"), IOStandard("LVTTL")),
("ttl", 6, Pins("LPC:LA22_N"), IOStandard("LVTTL")),
("ttl", 7, Pins("LPC:LA26_N"), IOStandard("LVTTL")),
("ttl", 8, Pins("LPC:LA23_P"), IOStandard("LVTTL")),
("ttl", 9, Pins("LPC:LA27_P"), IOStandard("LVTTL")),
("ttl", 10, Pins("LPC:LA23_N"), IOStandard("LVTTL")),
("ttl", 11, Pins("LPC:LA27_N"), IOStandard("LVTTL")),
("ttl", 12, Pins("LPC:LA00_CC_P"), IOStandard("LVTTL")),
("ttl", 13, Pins("LPC:LA10_P"), IOStandard("LVTTL")),
("ttl", 14, Pins("LPC:LA00_CC_N"), IOStandard("LVTTL")),
("ttl", 15, Pins("LPC:LA10_N"), IOStandard("LVTTL")),
("ttl_l_tx_en", 0, Pins("LPC:LA11_P"), IOStandard("LVTTL")),
("ttl_h_tx_en", 0, Pins("LPC:LA01_CC_P"), IOStandard("LVTTL")),
("dds", 0,
Subsignal("a", Pins("LPC:LA04_N LPC:LA14_N LPC:LA05_P LPC:LA15_P "
"LPC:LA05_N LPC:LA15_N")),
Subsignal("d", Pins("LPC:LA06_P LPC:LA16_P LPC:LA06_N LPC:LA16_N "
"LPC:LA07_P LPC:LA17_CC_P LPC:LA07_N "
"LPC:LA17_CC_N")),
Subsignal("sel", Pins("LPC:LA12_N LPC:LA03_P LPC:LA13_P LPC:LA03_N "
"LPC:LA13_N")),
Subsignal("p", Pins("LPC:LA11_N LPC:LA02_P")),
Subsignal("fud_n", Pins("LPC:LA14_P")),
Subsignal("wr_n", Pins("LPC:LA04_P")),
Subsignal("rd_n", Pins("LPC:LA02_N")),
Subsignal("rst_n", Pins("LPC:LA12_P")),
IOStandard("LVTTL")),
]
class _RTIOCRG(Module, AutoCSR): class _RTIOCRG(Module, AutoCSR):
@ -68,7 +28,7 @@ class _RTIOCRG(Module, AutoCSR):
o_O=self.cd_rtio.clk) o_O=self.cd_rtio.clk)
class _ARTIQSoCPeripherals(BaseSoC): class _Peripherals(BaseSoC):
csr_map = { csr_map = {
"rtio": None, # mapped on Wishbone instead "rtio": None, # mapped on Wishbone instead
"rtiocrg": 13 "rtiocrg": 13
@ -78,7 +38,7 @@ class _ARTIQSoCPeripherals(BaseSoC):
def __init__(self, platform, cpu_type="or1k", **kwargs): def __init__(self, platform, cpu_type="or1k", **kwargs):
BaseSoC.__init__(self, platform, BaseSoC.__init__(self, platform,
cpu_type=cpu_type, **kwargs) cpu_type=cpu_type, **kwargs)
platform.add_extension(_tester_io) platform.add_extension(nist_qc1.fmc_adapter_io)
self.submodules.leds = gpio.GPIOOut(Cat( self.submodules.leds = gpio.GPIOOut(Cat(
platform.request("user_led", 0), platform.request("user_led", 0),
@ -107,9 +67,9 @@ class _ARTIQSoCPeripherals(BaseSoC):
self.comb += dds_pads.fud_n.eq(~fud) self.comb += dds_pads.fud_n.eq(~fud)
class ARTIQSoCBasic(_ARTIQSoCPeripherals): class UP(_Peripherals):
def __init__(self, *args, **kwargs): def __init__(self, *args, **kwargs):
_ARTIQSoCPeripherals.__init__(self, *args, **kwargs) _Peripherals.__init__(self, *args, **kwargs)
rtio_csrs = self.rtio.get_csrs() rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs) self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
@ -119,14 +79,14 @@ class ARTIQSoCBasic(_ARTIQSoCPeripherals):
self.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus) self.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
class ARTIQSoC(_ARTIQSoCPeripherals): class AMP(_Peripherals):
csr_map = { csr_map = {
"kernel_cpu": 14 "kernel_cpu": 14
} }
csr_map.update(_ARTIQSoCPeripherals.csr_map) csr_map.update(_Peripherals.csr_map)
def __init__(self, platform, *args, **kwargs): def __init__(self, platform, *args, **kwargs):
_ARTIQSoCPeripherals.__init__(self, platform, *args, **kwargs) _Peripherals.__init__(self, platform, *args, **kwargs)
self.submodules.kernel_cpu = amp.KernelCPU( self.submodules.kernel_cpu = amp.KernelCPU(
platform, self.sdram.crossbar.get_master()) platform, self.sdram.crossbar.get_master())
@ -142,4 +102,4 @@ class ARTIQSoC(_ARTIQSoCPeripherals):
self.kernel_cpu.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus) self.kernel_cpu.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
default_subtarget = ARTIQSoCBasic default_subtarget = UP

60
soc/targets/artiq_pipistrello.py
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@ -1,54 +1,12 @@
from migen.fhdl.std import * from migen.fhdl.std import *
from migen.bank.description import * from migen.bank.description import *
from migen.bank import wbgen from migen.bank import wbgen
from mibuild.generic_platform import *
from misoclib.com import gpio from misoclib.com import gpio
from misoclib.soc import mem_decoder from misoclib.soc import mem_decoder
from targets.pipistrello import BaseSoC from targets.pipistrello import BaseSoC
from artiq.gateware import amp, rtio, ad9858 from artiq.gateware import amp, rtio, ad9858, nist_qc1
_tester_io = [
("ext_led", 0, Pins("B:7"), IOStandard("LVTTL")),
("pmt", 0, Pins("C:13"), IOStandard("LVTTL")),
("pmt", 1, Pins("C:14"), IOStandard("LVTTL")),
("xtrig", 0, Pins("C:12"), IOStandard("LVTTL")),
("dds_clock", 0, Pins("C:15"), IOStandard("LVTTL")),
("ttl", 0, Pins("C:11"), IOStandard("LVTTL")),
("ttl", 1, Pins("C:10"), IOStandard("LVTTL")),
("ttl", 2, Pins("C:9"), IOStandard("LVTTL")),
("ttl", 3, Pins("C:8"), IOStandard("LVTTL")),
("ttl", 4, Pins("C:7"), IOStandard("LVTTL")),
("ttl", 5, Pins("C:6"), IOStandard("LVTTL")),
("ttl", 6, Pins("C:5"), IOStandard("LVTTL")),
("ttl", 7, Pins("C:4"), IOStandard("LVTTL")),
("ttl_l_tx_en", 0, Pins("A:9"), IOStandard("LVTTL")),
("ttl", 8, Pins("C:3"), IOStandard("LVTTL")),
("ttl", 9, Pins("C:2"), IOStandard("LVTTL")),
("ttl", 10, Pins("C:1"), IOStandard("LVTTL")),
("ttl", 11, Pins("C:0"), IOStandard("LVTTL")),
("ttl", 12, Pins("B:4"), IOStandard("LVTTL")),
("ttl", 13, Pins("A:11"), IOStandard("LVTTL")),
("ttl", 14, Pins("B:5"), IOStandard("LVTTL")),
("ttl", 15, Pins("A:10"), IOStandard("LVTTL")),
("ttl_h_tx_en", 0, Pins("B:6"), IOStandard("LVTTL")),
("dds", 0,
Subsignal("a", Pins("A:5 B:10 A:6 B:9 A:7 B:8")),
Subsignal("d", Pins("A:12 B:3 A:13 B:2 A:14 B:1 A:15 B:0")),
Subsignal("sel", Pins("A:2 B:14 A:1 B:15 A:0")),
Subsignal("p", Pins("A:8 B:12")),
Subsignal("fud_n", Pins("B:11")),
Subsignal("wr_n", Pins("A:4")),
Subsignal("rd_n", Pins("B:13")),
Subsignal("rst_n", Pins("A:3")),
IOStandard("LVTTL")),
]
class _RTIOCRG(Module, AutoCSR): class _RTIOCRG(Module, AutoCSR):
@ -87,7 +45,7 @@ TIMESPEC "TSfix_ise2" = FROM "GRPsys_clk" TO "GRPrtio_clk" TIG;
""", rtio_clk=rtio_internal_clk) """, rtio_clk=rtio_internal_clk)
class _QcAdapterBase(BaseSoC): class _Peripherals(BaseSoC):
csr_map = { csr_map = {
"rtio": None, # mapped on Wishbone instead "rtio": None, # mapped on Wishbone instead
"rtiocrg": 13 "rtiocrg": 13
@ -96,7 +54,7 @@ class _QcAdapterBase(BaseSoC):
def __init__(self, platform, cpu_type="or1k", **kwargs): def __init__(self, platform, cpu_type="or1k", **kwargs):
BaseSoC.__init__(self, platform, cpu_type=cpu_type, **kwargs) BaseSoC.__init__(self, platform, cpu_type=cpu_type, **kwargs)
platform.add_extension(_tester_io) platform.add_extension(nist_qc1.papilio_adapter_io)
self.submodules.leds = gpio.GPIOOut(Cat( self.submodules.leds = gpio.GPIOOut(Cat(
platform.request("user_led", 0), platform.request("user_led", 0),
@ -128,9 +86,9 @@ class _QcAdapterBase(BaseSoC):
self.comb += dds_pads.fud_n.eq(~fud) self.comb += dds_pads.fud_n.eq(~fud)
class Single(_QcAdapterBase): class UP(_Peripherals):
def __init__(self, platform, **kwargs): def __init__(self, platform, **kwargs):
_QcAdapterBase.__init__(self, platform, **kwargs) _Peripherals.__init__(self, platform, **kwargs)
rtio_csrs = self.rtio.get_csrs() rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs) self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
@ -140,14 +98,14 @@ class Single(_QcAdapterBase):
self.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus) self.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
class Double(_QcAdapterBase): class AMP(_Peripherals):
csr_map = { csr_map = {
"kernel_cpu": 14 "kernel_cpu": 14
} }
csr_map.update(_QcAdapterBase.csr_map) csr_map.update(_Peripherals.csr_map)
def __init__(self, platform, *args, **kwargs): def __init__(self, platform, *args, **kwargs):
_QcAdapterBase.__init__(self, platform, **kwargs) _Peripherals.__init__(self, platform, **kwargs)
self.submodules.kernel_cpu = amp.KernelCPU( self.submodules.kernel_cpu = amp.KernelCPU(
platform, self.sdram.crossbar.get_master()) platform, self.sdram.crossbar.get_master())
@ -163,4 +121,4 @@ class Double(_QcAdapterBase):
self.kernel_cpu.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus) self.kernel_cpu.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
default_subtarget = Single default_subtarget = UP

44
soc/targets/artiq_ppro.py
View File

@ -7,40 +7,7 @@ from misoclib.com import gpio
from misoclib.mem.sdram.core.minicon import MiniconSettings from misoclib.mem.sdram.core.minicon import MiniconSettings
from targets.ppro import BaseSoC from targets.ppro import BaseSoC
from artiq.gateware import rtio, ad9858 from artiq.gateware import rtio, ad9858, nist_qc1
_tester_io = [
("user_led", 1, Pins("B:7"), IOStandard("LVTTL")),
("pmt", 0, Pins("C:13"), IOStandard("LVTTL")),
("pmt", 1, Pins("C:14"), IOStandard("LVTTL")),
("xtrig", 0, Pins("C:12"), IOStandard("LVTTL")), # used for DDS clock
("ttl", 0, Pins("C:11"), IOStandard("LVTTL")),
("ttl", 1, Pins("C:10"), IOStandard("LVTTL")),
("ttl", 2, Pins("C:9"), IOStandard("LVTTL")),
("ttl", 3, Pins("C:8"), IOStandard("LVTTL")),
("ttl", 4, Pins("C:7"), IOStandard("LVTTL")),
("ttl", 5, Pins("C:6"), IOStandard("LVTTL")),
("ttl", 6, Pins("C:5"), IOStandard("LVTTL")),
("ttl", 7, Pins("C:4"), IOStandard("LVTTL")),
("ttl_l_tx_en", 0, Pins("A:9"), IOStandard("LVTTL")),
("ttl", 8, Pins("C:3"), IOStandard("LVTTL")),
("ttl_h_tx_en", 0, Pins("B:6"), IOStandard("LVTTL")),
("dds", 0,
Subsignal("a", Pins("A:5 B:10 A:6 B:9 A:7 B:8")),
Subsignal("d", Pins("A:12 B:3 A:13 B:2 A:14 B:1 A:15 B:0")),
Subsignal("sel", Pins("A:2 B:14 A:1 B:15 A:0")),
Subsignal("p", Pins("A:8 B:12")),
Subsignal("fud_n", Pins("B:11")),
Subsignal("wr_n", Pins("A:4")),
Subsignal("rd_n", Pins("B:13")),
Subsignal("rst_n", Pins("A:3")),
IOStandard("LVTTL")),
]
class _TestGen(Module): class _TestGen(Module):
@ -86,7 +53,7 @@ TIMESPEC "TSfix_ise2" = FROM "GRPsys_clk" TO "GRPrtio_clk" TIG;
""", rtio_clk=rtio_internal_clk) """, rtio_clk=rtio_internal_clk)
class ARTIQMiniSoC(BaseSoC): class UP(BaseSoC):
csr_map = { csr_map = {
"rtio": None, # mapped on Wishbone instead "rtio": None, # mapped on Wishbone instead
"rtiocrg": 13 "rtiocrg": 13
@ -99,11 +66,11 @@ class ARTIQMiniSoC(BaseSoC):
cpu_type=cpu_type, cpu_type=cpu_type,
sdram_controller_settings=MiniconSettings(), sdram_controller_settings=MiniconSettings(),
**kwargs) **kwargs)
platform.add_extension(_tester_io) platform.add_extension(nist_qc1.papilio_adapter_io)
self.submodules.leds = gpio.GPIOOut(Cat( self.submodules.leds = gpio.GPIOOut(Cat(
platform.request("user_led", 0), platform.request("user_led", 0),
platform.request("user_led", 1))) platform.request("ext_led", 0)))
fud = Signal() fud = Signal()
self.comb += [ self.comb += [
@ -135,4 +102,5 @@ class ARTIQMiniSoC(BaseSoC):
self.add_wb_slave(lambda a: a[26:29] == 3, self.dds.bus) self.add_wb_slave(lambda a: a[26:29] == 3, self.dds.bus)
self.comb += dds_pads.fud_n.eq(~fud) self.comb += dds_pads.fud_n.eq(~fud)
default_subtarget = ARTIQMiniSoC
default_subtarget = UP