forked from M-Labs/artiq
Merge branch 'pipistrello-analyzer' into ppp
* pipistrello-analyzer: pipistrello: add rtio.Analyzer()
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commit
7e3610c545
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@ -106,7 +106,8 @@ class NIST_QC1(BaseSoC, AMPSoC):
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"rtio": None, # mapped on Wishbone instead
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"rtio": None, # mapped on Wishbone instead
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"rtio_crg": 10,
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"rtio_crg": 10,
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"kernel_cpu": 11,
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"kernel_cpu": 11,
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"rtio_moninj": 12
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"rtio_moninj": 12,
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"rtio_analyzer": 13
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}
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}
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csr_map.update(BaseSoC.csr_map)
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csr_map.update(BaseSoC.csr_map)
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mem_map = {
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mem_map = {
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@ -208,6 +209,9 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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self.add_csr_region("rtio", self.mem_map["rtio"] | 0x80000000, 32,
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self.add_csr_region("rtio", self.mem_map["rtio"] | 0x80000000, 32,
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rtio_csrs)
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rtio_csrs)
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self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio,
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self.get_native_sdram_if())
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def main():
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def main():
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parser = argparse.ArgumentParser(
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parser = argparse.ArgumentParser(
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