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kasli: false paths 

* don't bother with the round trip OSERDESE2 -> ... -> pad -> ... ->
  ISERDESE2
* clock groups with derived clocks c.f. migen 9c3a301
This commit is contained in:
Robert Jördens 2018-02-19 13:05:11 +00:00
parent 0f4549655b
commit 7e02d8245c
1 changed files with 11 additions and 1 deletions
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12
artiq/gateware/targets/kasli.py
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@ -44,6 +44,8 @@ class _RTIOCRG(Module, AutoCSR):
i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se), i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se),
Instance("BUFG", i_I=clk_synth_se, o_O=rtio_external_clk), Instance("BUFG", i_I=clk_synth_se, o_O=rtio_external_clk),
] ]
platform.add_false_path_constraints(
rtio_external_clk, rtio_internal_clk)
pll_locked = Signal() pll_locked = Signal()
rtio_clk = Signal() rtio_clk = Signal()
@ -124,7 +126,6 @@ class _StandaloneBase(MiniSoC, AMPSoC):
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj") self.csr_devices.append("rtio_moninj")
self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
self.platform.add_false_path_constraints( self.platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.crg.cd_sys.clk,
self.rtio_crg.cd_rtio.clk) self.rtio_crg.cd_rtio.clk)
@ -133,6 +134,15 @@ class _StandaloneBase(MiniSoC, AMPSoC):
self.get_native_sdram_if()) self.get_native_sdram_if())
self.csr_devices.append("rtio_analyzer") self.csr_devices.append("rtio_analyzer")
# ignore timing of path from OSERDESE2 through the pad to ISERDESE2
self.platform.add_platform_command(
"set_false_path -quiet "
"-through [get_pins -filter {{REF_PIN_NAME == OQ || REF_PIN_NAME == TQ}} "
"-of [get_cells -filter {{REF_NAME == OSERDESE2}}]] "
"-to [get_pins -filter {{REF_PIN_NAME == D}} "
"-of [get_cells -filter {{REF_NAME == ISERDESE2}}]]"
)
def _eem_signal(i): def _eem_signal(i):
n = "d{}".format(i) n = "d{}".format(i)