forked from M-Labs/artiq
kasli: false paths
* don't bother with the round trip OSERDESE2 -> ... -> pad -> ... -> ISERDESE2 * clock groups with derived clocks c.f. migen 9c3a301
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@ -44,6 +44,8 @@ class _RTIOCRG(Module, AutoCSR):
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i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se),
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Instance("BUFG", i_I=clk_synth_se, o_O=rtio_external_clk),
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]
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platform.add_false_path_constraints(
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rtio_external_clk, rtio_internal_clk)
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pll_locked = Signal()
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rtio_clk = Signal()
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@ -124,7 +126,6 @@ class _StandaloneBase(MiniSoC, AMPSoC):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.rtio_crg.cd_rtio.clk)
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@ -133,6 +134,15 @@ class _StandaloneBase(MiniSoC, AMPSoC):
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self.get_native_sdram_if())
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self.csr_devices.append("rtio_analyzer")
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# ignore timing of path from OSERDESE2 through the pad to ISERDESE2
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self.platform.add_platform_command(
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"set_false_path -quiet "
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"-through [get_pins -filter {{REF_PIN_NAME == OQ || REF_PIN_NAME == TQ}} "
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"-of [get_cells -filter {{REF_NAME == OSERDESE2}}]] "
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"-to [get_pins -filter {{REF_PIN_NAME == D}} "
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"-of [get_cells -filter {{REF_NAME == ISERDESE2}}]]"
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)
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def _eem_signal(i):
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n = "d{}".format(i)
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