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hmc7043: make margin_{minus,plus} consistent with ad9154

This commit is contained in:
Sebastien Bourdeauducq 2018-06-27 17:35:26 +08:00
parent 4bbdd43bdf
commit 7dfd70c502
1 changed files with 6 additions and 7 deletions
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13
artiq/firmware/libboard_artiq/hmc830_7043.rs
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@ -382,24 +382,23 @@ pub mod hmc7043 {
}
info!(" ...done ({}/{} slips), verifying timing margin", slips0, slips1);
let mut margin_plus = None;
let mut margin_minus = None;
for d in 0..phase_offset {
sysref_offset_fpga(phase_offset - d);
if !sysref_sample() {
margin_plus = Some(d);
margin_minus = Some(d);
break;
}
}
// meet setup/hold
sysref_offset_fpga(phase_offset);
if margin_plus.is_some() {
let margin_plus = margin_plus.unwrap();
if margin_minus.is_some() {
let margin_minus = margin_minus.unwrap();
// one phase slip (period of the 1.2GHz input clock)
let period = 2*17; // approximate: 2 digital coarse delay steps
let margin_minus = if period > margin_plus { period - margin_plus } else { 0 };
info!(" margin at FPGA: -{} +{}", margin_minus, margin_plus);
let margin_plus = if period > margin_minus { period - margin_minus } else { 0 };
info!(" margins at FPGA: -{} +{}", margin_minus, margin_plus);
if margin_minus < 10 || margin_plus < 10 {
error!("SYSREF margin at FPGA is too small");
}