From 7dfd70c5022980a19872109a5fe2632d3e8f7525 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 27 Jun 2018 17:35:26 +0800 Subject: [PATCH] hmc7043: make margin_{minus,plus} consistent with ad9154 --- artiq/firmware/libboard_artiq/hmc830_7043.rs | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/artiq/firmware/libboard_artiq/hmc830_7043.rs b/artiq/firmware/libboard_artiq/hmc830_7043.rs index 1446d9cbb..e41ae9361 100644 --- a/artiq/firmware/libboard_artiq/hmc830_7043.rs +++ b/artiq/firmware/libboard_artiq/hmc830_7043.rs @@ -382,24 +382,23 @@ pub mod hmc7043 { } info!(" ...done ({}/{} slips), verifying timing margin", slips0, slips1); - let mut margin_plus = None; + let mut margin_minus = None; for d in 0..phase_offset { sysref_offset_fpga(phase_offset - d); if !sysref_sample() { - margin_plus = Some(d); + margin_minus = Some(d); break; } } - // meet setup/hold sysref_offset_fpga(phase_offset); - if margin_plus.is_some() { - let margin_plus = margin_plus.unwrap(); + if margin_minus.is_some() { + let margin_minus = margin_minus.unwrap(); // one phase slip (period of the 1.2GHz input clock) let period = 2*17; // approximate: 2 digital coarse delay steps - let margin_minus = if period > margin_plus { period - margin_plus } else { 0 }; - info!(" margin at FPGA: -{} +{}", margin_minus, margin_plus); + let margin_plus = if period > margin_minus { period - margin_minus } else { 0 }; + info!(" margins at FPGA: -{} +{}", margin_minus, margin_plus); if margin_minus < 10 || margin_plus < 10 { error!("SYSREF margin at FPGA is too small"); }