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drtio: fix syntax/import

This commit is contained in:
Sebastien Bourdeauducq 2017-01-30 13:01:45 +08:00
parent d8e9949266
commit 7daab07a29
1 changed files with 8 additions and 7 deletions
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15
artiq/gateware/targets/kc705_drtio_satellite.py
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@ -5,6 +5,7 @@ from migen import *
from migen.build.generic_platform import * from migen.build.generic_platform import *
from misoc.cores.i2c import * from misoc.cores.i2c import *
from misoc.cores.sequencer import * from misoc.cores.sequencer import *
from misoc.cores import spi as spi_csr
from misoc.integration.builder import * from misoc.integration.builder import *
from misoc.integration.soc_core import mem_decoder from misoc.integration.soc_core import mem_decoder
from misoc.targets.kc705 import BaseSoC, soc_kc705_args, soc_kc705_argdict from misoc.targets.kc705 import BaseSoC, soc_kc705_args, soc_kc705_argdict
@ -176,13 +177,13 @@ class Satellite(BaseSoC):
rx_pads=rx_pads, rx_pads=rx_pads,
sys_clk_freq=self.clk_freq) sys_clk_freq=self.clk_freq)
ad9154_spi = platform.request("ad9154_spi") ad9154_spi = platform.request("ad9154_spi")
self.comb += ad9154_spi.en.eq(1) self.comb += ad9154_spi.en.eq(1)
self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi) self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
self.csr_devices.append("converter_spi") self.csr_devices.append("converter_spi")
self.config["CONVERTER_SPI_DAC_CS"] = 0 self.config["CONVERTER_SPI_DAC_CS"] = 0
self.config["CONVERTER_SPI_CLK_CS"] = 1 self.config["CONVERTER_SPI_CLK_CS"] = 1
self.config["HAS_AD9516"] = None self.config["HAS_AD9516"] = None
else: else:
raise ValueError raise ValueError
self.submodules.rx_synchronizer = gtx_7series.RXSynchronizer( self.submodules.rx_synchronizer = gtx_7series.RXSynchronizer(