forked from M-Labs/artiq
runtime/rt2wb: use input/output terminology and add (async) input
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764795a8fe
commit
7d7a710a56
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@ -3,12 +3,16 @@ from artiq.language.types import *
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@syscall
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def rt2wb_write(time_mu: TInt64, channel: TInt32, addr: TInt32, data: TInt32
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) -> TNone:
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def rt2wb_output(time_mu: TInt64, channel: TInt32, addr: TInt32, data: TInt32
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) -> TNone:
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raise NotImplementedError("syscall not simulated")
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@syscall
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def rt2wb_read_sync(time_mu: TInt64, channel: TInt32, addr: TInt32,
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duration_mu: TInt32) -> TInt32:
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def rt2wb_input(channel: TInt32) -> TInt32:
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raise NotImplementedError("syscall not simulated")
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@syscall
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def rt2wb_input_sync(timeout_mu: TInt64, channel: TInt32) -> TInt32:
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raise NotImplementedError("syscall not simulated")
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@ -1,7 +1,7 @@
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from artiq.language.core import (kernel, portable, seconds_to_mu, now_mu,
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delay_mu)
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delay_mu, int)
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from artiq.language.units import MHz
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from artiq.coredevice.rt2wb import rt2wb_write, rt2wb_read_sync
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from artiq.coredevice.rt2wb import rt2wb_output, rt2wb_input, rt2wb_input_sync
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SPI_DATA_ADDR, SPI_XFER_ADDR, SPI_CONFIG_ADDR = range(3)
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@ -28,11 +28,11 @@ class SPIMaster:
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def __init__(self, dmgr, ref_period, channel):
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self.core = dmgr.get("core")
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self.ref_period = ref_period
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self.ref_period_mu = seconds_to_mu(ref_period, self.core)
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self.ref_period_mu = int(seconds_to_mu(ref_period, self.core))
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self.channel = channel
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self.write_period_mu = 0
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self.read_period_mu = 0
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self.xfer_period_mu = 0
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self.write_period_mu = int(0)
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self.read_period_mu = int(0)
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self.xfer_period_mu = int(0)
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# A full transfer takes write_period_mu + xfer_period_mu.
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# Chained transfers can happen every xfer_period_mu.
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# The second transfer of a chain can be written 2*ref_period_mu
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@ -49,11 +49,11 @@ class SPIMaster:
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@kernel
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def set_config_mu(self, flags=0, write_div=6, read_div=6):
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rt2wb_write(now_mu(), self.channel, SPI_CONFIG_ADDR, flags |
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((write_div - 2) << 16) | ((read_div - 2) << 24))
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rt2wb_output(now_mu(), self.channel, SPI_CONFIG_ADDR, flags |
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((write_div - 2) << 16) | ((read_div - 2) << 24))
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self.write_period_mu = int(write_div*self.ref_period_mu)
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self.read_period_mu = int(read_div*self.ref_period_mu)
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delay_mu(2*self.ref_period_mu)
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delay_mu(3*self.ref_period_mu)
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@portable
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def get_xfer_period_mu(self, write_length, read_length):
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@ -62,33 +62,40 @@ class SPIMaster:
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@kernel
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def set_xfer(self, chip_select=0, write_length=0, read_length=0):
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rt2wb_write(now_mu(), self.channel, SPI_XFER_ADDR,
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chip_select | (write_length << 16) | (read_length << 24))
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self.xfer_period_mu = self.get_xfer_period_mu(
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write_length, read_length)
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delay_mu(int(2*self.ref_period_mu))
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rt2wb_output(now_mu(), self.channel, SPI_XFER_ADDR,
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chip_select | (write_length << 16) | (read_length << 24))
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self.xfer_period_mu = self.get_xfer_period_mu(write_length,
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read_length)
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delay_mu(3*self.ref_period_mu)
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@kernel
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def write(self, data):
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rt2wb_write(now_mu(), self.channel, SPI_DATA_ADDR, data)
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delay_mu(int(self.write_period_mu + self.xfer_period_mu))
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rt2wb_output(now_mu(), self.channel, SPI_DATA_ADDR, data)
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delay_mu(3*self.ref_period_mu)
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@kernel
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def read_async(self):
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rt2wb_write(now_mu(), self.channel, SPI_DATA_ADDR | SPI_RT2WB_READ, 0)
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delay_mu(int(2*self.ref_period_mu))
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def read(self):
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rt2wb_output(now_mu(), self.channel, SPI_DATA_ADDR | SPI_RT2WB_READ, 0)
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delay_mu(3*self.ref_period_mu)
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@kernel
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def input(self):
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return rt2wb_input(self.channel)
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@kernel
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def _rt2wb_read_sync(self, addr=0):
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t = now_mu()
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rt2wb_output(t, self.channel, addr | SPI_RT2WB_READ, 0)
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return rt2wb_input_sync(t + 3*self.ref_period_mu, self.channel)
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@kernel
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def read_sync(self):
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return rt2wb_read_sync(now_mu(), self.channel, SPI_DATA_ADDR |
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SPI_RT2WB_READ, int(2*self.ref_period_mu))
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return self._rt2wb_read_sync(SPI_DATA_ADDR)
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@kernel
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def _get_config_sync(self):
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return rt2wb_read_sync(now_mu(), self.channel, SPI_CONFIG_ADDR |
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SPI_RT2WB_READ, int(2*self.ref_period_mu))
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return self._rt2wb_read_sync(SPI_CONFIG_ADDR)
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@kernel
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def _get_xfer_sync(self):
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return rt2wb_read_sync(now_mu(), self.channel, SPI_XFER_ADDR |
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SPI_RT2WB_READ, int(2*self.ref_period_mu))
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return self._rt2wb_read_sync(SPI_XFER_ADDR)
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@ -26,7 +26,7 @@
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#endif
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#define DDS_WRITE(addr, data) do { \
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rt2wb_write(now, CONFIG_RTIO_DDS_CHANNEL, addr, data); \
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rt2wb_output(now, CONFIG_RTIO_DDS_CHANNEL, addr, data); \
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now += DURATION_WRITE; \
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} while(0)
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@ -122,8 +122,9 @@ static const struct symbol runtime_exports[] = {
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{"dds_batch_exit", &dds_batch_exit},
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{"dds_set", &dds_set},
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{"rt2wb_write", &rt2wb_write},
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{"rt2wb_read_sync", &rt2wb_read_sync},
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{"rt2wb_output", &rt2wb_output},
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{"rt2wb_input", &rt2wb_input},
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{"rt2wb_input_sync", &rt2wb_input_sync},
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{"cache_get", &cache_get},
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{"cache_put", &cache_put},
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@ -5,29 +5,50 @@
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#include "rt2wb.h"
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void rt2wb_write(long long int timestamp, int channel, int addr,
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void rt2wb_output(long long int timestamp, int channel, int addr,
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unsigned int data)
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{
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rtio_output(timestamp, channel, addr, data);
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}
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unsigned int rt2wb_read_sync(long long int timestamp, int channel, int addr,
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int duration)
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unsigned int rt2wb_input(int channel)
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{
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unsigned int data;
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int status;
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rtio_output(timestamp, channel, addr, 0);
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status = rtio_input_wait(timestamp + duration, channel);
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if (status & RTIO_I_STATUS_OVERFLOW)
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rtio_chan_sel_write(channel);
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status = rtio_i_status_read();
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if (status & RTIO_I_STATUS_OVERFLOW) {
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rtio_i_overflow_reset_write(1);
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artiq_raise_from_c("RTIOOverflow",
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"RT2WB read overflow on channel {0}",
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"RT2WB input overflow on channel {0}",
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channel, 0, 0);
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}
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if (status & RTIO_I_STATUS_EMPTY)
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artiq_raise_from_c("RTIOTimeout",
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"RT2WB read timeout on channel {0}",
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"RT2WB input timeout on channel {0}",
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channel, 0, 0);
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data = rtio_i_data_read();
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rtio_i_re_write(1);
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return data;
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}
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unsigned int rt2wb_input_sync(long long int timeout, int channel)
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{
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unsigned int data;
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int status;
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status = rtio_input_wait(timeout, channel);
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if (status & RTIO_I_STATUS_OVERFLOW)
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artiq_raise_from_c("RTIOOverflow",
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"RT2WB input overflow on channel {0}",
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channel, 0, 0);
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if (status & RTIO_I_STATUS_EMPTY)
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artiq_raise_from_c("RTIOTimeout",
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"RT2WB input timeout on channel {0}",
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channel, 0, 0);
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data = rtio_i_data_read();
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@ -3,10 +3,10 @@
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#include "rtio.h"
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void rt2wb_write(long long int timestamp, int channel, int address,
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void rt2wb_output(long long int timestamp, int channel, int addr,
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unsigned int data);
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unsigned int rt2wb_read_sync(long long int timestamp, int channel, int address,
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int duration);
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unsigned int rt2wb_input(int channel);
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unsigned int rt2wb_input_sync(long long int timeout, int channel);
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#endif /* __RT2WB_H */
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