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drtio: add support for 125MHz clock on GTX_1000BASE_BX10

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Sebastien Bourdeauducq 2016-10-29 17:30:29 +08:00
parent 95def81c03
commit 7c05dccf65
1 changed files with 18 additions and 7 deletions
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25
artiq/gateware/drtio/transceiver/gtx_7series.py
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@ -10,7 +10,10 @@ from artiq.gateware.drtio.transceiver.gtx_7series_init import *
class GTX_1000BASE_BX10(Module): class GTX_1000BASE_BX10(Module):
rtio_clk_freq = 62.5e6 rtio_clk_freq = 62.5e6
def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq): # The transceiver clock on clock_pads must be 62.5MHz
# when clock_div2=False, and 125MHz when clock_div2=True.
def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq,
clock_div2=False):
self.submodules.encoder = ClockDomainsRenamer("rtio")( self.submodules.encoder = ClockDomainsRenamer("rtio")(
Encoder(2, True)) Encoder(2, True))
self.decoders = [ClockDomainsRenamer("rtio_rx")( self.decoders = [ClockDomainsRenamer("rtio_rx")(
@ -23,12 +26,20 @@ class GTX_1000BASE_BX10(Module):
# # # # # #
refclk = Signal() refclk = Signal()
self.specials += Instance("IBUFDS_GTE2", if clock_div2:
i_CEB=0, self.specials += Instance("IBUFDS_GTE2",
i_I=clock_pads.p, i_CEB=0,
i_IB=clock_pads.n, i_I=clock_pads.p,
o_O=refclk i_IB=clock_pads.n,
) o_ODIV2=refclk
)
else:
self.specials += Instance("IBUFDS_GTE2",
i_CEB=0,
i_I=clock_pads.p,
i_IB=clock_pads.n,
o_O=refclk
)
cplllock = Signal() cplllock = Signal()
# TX generates RTIO clock, init must be in system domain # TX generates RTIO clock, init must be in system domain